Perr; The Command And Byte Enable Bits Cbe[3:0]; Address Phase Cbe[3:0] Values - Adaptec AIC-6915 Programmer's Manual

PERR_

The AIC-6915 asserts
PERR_
As a target device, the AIC-6915 asserts
register in PCI Configuration header) for write cycles in which it detects a data parity
error, only if it claims the access and asserts
period for each detected error two PCLK periods after the Data phase that contained the
error.
As a master, the AIC-6915 asserts
which it detects a data parity error. The AIC-6915 asserts
initiates.

The Command And Byte Enable Bits CBE[3:0]_

The Bus Command and Byte Enable bits are multiplexed on the same PCI pins. During the
address phase of a transaction,
to be performed during the transaction. Table 4-3 describes how the AIC-6915 responds to
different commands.
Command
CBE [3:0]_ Abbrev.
0000 IAC
0001 SSC
0010 IORDC
0011 IOWRC
0100 RSVD
0101 RSVD
0110 MRDC
0111 MWRC
1000 RSVD
1001 RSVD
1010 CRDC
1011 CWRC
1100 MRDMC
1101 DAC
1110 MRDLC
1111 MWRIC
1
Defaults to Memory Read
2
Defaults to Memory Write
The values accepted during a Data phase indicate the valid data bytes. The PCI
CBE[3:0]_
target supports any combination of byte enables.
for detected data parity errors only if
and sets the DPE bit active (
PERR_
DEVSEL_. PERR_
, and sets DPE (PCI header) for read cycles in
PERR_
contain a Bus command that defines the function
CBE[3:0]_
Table 4-3. Address Phase CBE[3:0] Values
Type
Interrupt Acknowledge
Special Cycle
I/O Read
I/O Write
Memory Read
Memory Write
Configuration Read
Configuration Write
Memory Read Multiple
Dual Address Cycle
Memory Read Line
Memory Write and
Invalidate
PCI Module Architecture
is asserted.
PERRESPEN
STATUS
is asserted for one PCLK
only for cycles that it
PERR_
AIC-6915 Support
Target Master
No No
No No
Yes No
Yes No
No No
No No
Yes Yes
Yes Yes
No No
No No
Yes No
Yes No
1
Yes
No Yes
1
Yes
2
Yes
4-13