Pci Functional Registers Definition - Adaptec AIC-6915 Programmer's Manual

PCI Functional Registers Definition

The following registers are accessible from PCI configuration, memory and direct I/O
space.
PCIDeviceConfig Register
Type: R/W
Internal Registers Subgroup: PCI Functional Registers
Byte Address: 40h - 43h
Reset
Bit(s) rw Value
31 r/w 0
30 r/w 0
29 r/w 0
28 r/w 0
27 r/w 0
26:25 r 0
24 r/w 0
23 r/w 0
22:20 r/w 0
19 r/w 0
Table 7-27. PCIDeviceConfig Register
Description/Function
EnDpeInt: Enables assertion of DPE (in PCI Configuration Header
Status register) to set PCIInt. PCIInt is an internal interrupt status
bit implemented in InterruptStatus register.
EnSseInt: Enables assertion SSE (in PCI Configuration Header
Status register) to set PCIInt.
EnRmaInt: Enables assertion RMA (in PCI Configuration Header
Status register) to set PCIInt.
EnRtaInt: Enables assertion RTA (in PCI Configuration Header
Status register) to set PCIInt.
EnStaInt: Enables assertion STA (in PCI Configuration Header
Status register) to set PCIInt.
Reserved: Always read as 0.
EnDprInt: Enables assertion DPR (in PCI Configuration Header
Status register) to set PCIInt.
IntEnable: Setting this bit enables the device to assert a PCI
interrupt (PCI_INTA_), else PCI interrupt is disabled. This bit must
be set if the software driver wishes to receive any type of interrupts.
ExternalRegCsWidth: Indicates the width of the chip-select when
an access to an external register is performed.
'000' - 8 PCI clocks
'111' - 7 PCI clocks
'110' - 6 PCI clocks
'101' - 5 PCI clocks
'100' - 4 PCI clocks
'011' - 3 PCI clocks
All other combinations are reserved.
StopMWrOnCacheLineDis: When this bit is cleared, the AIC-6915
stops any memory write on a cacheline boundary if the remaining
number of data transfers is more than the cacheline size. A memory
write and invalidate cycle follows. When the bit is set this function is
disabled.
Register Descriptions
7-17