Adaptec 1737100 - 62044 SGL ENET PCI 4CH Manuals

Manuals and User Guides for Adaptec 1737100 - 62044 SGL ENET PCI 4CH. We have 1 Adaptec 1737100 - 62044 SGL ENET PCI 4CH manual available for free PDF download: Programmer's Manual

Adaptec 1737100 - 62044 SGL ENET PCI 4CH Programmer's Manual (190 pages)

Ethernet LAN Controller

Brand: Adaptec | Category: Controller | Size: 1 MB

Table of Contents
5
Document Title: Document Title Stock Number: XXXXXX-XX Rev
10
Print Spec Number: XXXXXX-XX Rev. X
10
Current Date: 10/10/98
10
Page: Front Matter-VII
10
ECN Date: XX/XX/XX
10
Introduction

15
- Features
  16
  - General
    16
  - Ethernet
    16
  - Dma
    16
  - Internal Buffer Management
    17
  - 32/64-Bit PCI
    17
- Block Diagram
  19
AIC-6915 Block Diagram

19
- Modules
  20
Receive Architecture

21
- Features
  21
- Host Data Structures
  22
  - Producer and Consumer Indices
    22
  - Receive DMA Descriptor Queues
    22
The AIC-6915 Receive Data Structures

22
- Normal Mode
  23
- Polling Mode
  23
- 32-Bit Addressing Mode
  24
- Completion/Status Descriptor Queue
  24
  - Accepting Frames
    25
    
    Completion Descriptor
    25
2-2 Receive Buffer Descriptor (One-Size Buffer, 64-Bit Addressing)2-4

26
2-1 Receive Buffer Descriptor (One-Size, 32-Bit Addressing)2-4

26
Transmit Architecture

31
- Features
  31
- Transmit Data Structure
  34
Transmit Host Communication Data Structure

34
- Transmit Register Set
  35
- Transmit DMA Buffer Descriptor Queues
  35
  - Type 0, 32-Bit Addressing Mode (Frame Descriptor)
    35
2-10 Receive Completion Descriptor (Word 3)2-9

36
2-9 Receive Completion Descriptor (Word 2)2-9

36
PCI Module Architecture

43
- Features
  43
- PCI Block Diagram
  
  45
  - PCI Master Module
    46
    
    64-Bit PCI Bus Master
    47
  - Bit PCI Reset Timing
    47
    
    Arbitration
    48
    
    PCI Target Module
    48
    
    Power Management
    50
    
    Power Management States
    50
    
    Cardbus
    51
    
    Response to PCI Commands
    51
    
    Retry Function
    51
    
    Target Response to PCI Commands
    52
    
    Configuration Address Space
    53
    
    I/O Address Space (Direct Access)
    53
    
    I/O Address Space (Indirect Access)
    53
    
    Expansion ROM Address Space
    54
    
    Memory Address Space
    54
    
    Parity
    54
    
    Serr
    54
    
    Address Phase CBE[3:0] Values
    55
    
    Perr
    55
    
    The Command and Byte Enable Bits CBE[3:0]
    55
    
    Illegal Behavior
    56
Frame Processor Architecture

57
- Features
  57
- General Architecture & Operation
  57
  - Wake-Up Mode
    58
  - Transmit Checksum Accelerator
    58
  - GFP Address Space
    59
    
    Internal Registers
    59
    
    Status/Control Register
    59
    
    External Registers
    60
4-2 64-Bit PCI Reset Timing4-5

61
- Block Diagram
  61
Data Processing Unit

61
- Instruction Formats
  62
AIC-6915 Internal Registers Summary

67
Register Descriptions

73
- Overview
  73
- Shade Legends
  73
- AIC-6915 Address Space
  74
- AIC-6915 PCI Address Map
  74
- AIC-6915 PCI Address Space
  74
AIC-6915 PCI Address Map

75
- Terminology
  76
- AIC-6915 Internal Registers
  76
  - PCI Registers
    77
    
    PCI Configuration Header Registers
    77
    
    PCI Device ID Register
    77
    
    PCI Vendor ID Register
    77
    
    Device Revision ID Register
    81
    
    Program Interface Register
    81
    
    Subclass Register
    81
    
    Baseclass Register
    82
    
    Cache Line Size Register
    82
    
    Latency Timer Register
    82
    
    Base Address 0 Register
    83
    
    BIST Register
    83
    
    Header Type Register
    83
    
    Base Address 1 Register
    84
    
    Configuration Card Information Structure Register
    84
    
    High Base Address 0 Register
    84
    
    Subsystem ID Register
    85
    
    Subsystemvendor ID Register
    85
    
    Capabilities List Pointer Register
    86
    
    Expansion ROM Control Register
    86
    
    Interrupt Line Select Register
    86
    
    Interrupt Pin Select Register
    87
    
    Minimum Grant Register
    87
    
    Maximum Latency Register
    88
    
    PCI Functional Registers Definition
    89
    
    Baccontrol Register
    92
    
    PCI Monitor1 Register
    93
    
    PCI Monitor2 Register
    94
    
    Power Management Register
    94
    
    Power Management Control Status Register
    95
    
    Eepromcontrolstatus Register
    96
    
    PME Event Register
    96
    
    EEPROM Memory Definition
    97
    
    Indirectioaddress Register
    98
    
    Indirectiodataport Register
    98
    
    Pcicompliancetesting Register
    98
  - Ethernet Registers
    99
    
    General Ethernet Functional Registers
    99
    
    Timerscontrol Register
    100
    
    Currenttime Register
    102
    
    Interruptstatus Register
    103
    
    PCI Status Register
    103
    
    Shadowinterruptstatus Register
    106
    
    Interrupten Register
    107
    
    Pcideviceconfig Register
    107
    
    GPIO Register
    108
    
    Transmit Registers
    109
    
    Txdescqueuectrl Register
    109
    
    Hiprtxdescqueuebaseaddress Register
    111
    
    Loprtxdescqueuebaseaddress Register
    111
    
    Txdescqueuehighaddr Register
    112
    
    Txdescqueueproducerindex Register
    112
    
    Txdescqueueconsumerindex Register
    113
    
    Txdmastatus1 Register
    113
    
    Transmitframecontrolstatus Register
    114
    
    Txdmastatus2 Register
    114
    
    Completion Queue Registers
    115
    
    Compqueuehighaddress Register
    115
    
    Txcompletionqueuectrl Register
    115
    
    Rxcompletionqueue2Ctrl Register
    117
    
    Completionqueueconsumerindex Register
    118
    
    Completionqueueproducerindex Register
    119
    
    Rxhiprcompletionptrs Register
    119
    
    Receive Registers
    120
    
    Rxdmactrl Register
    120
    
    Rxdescqueue1Ctrl Register
    122
    
    Rxdescqueue1Lowaddress Register
    124
    
    Rxdescqueue2Ctrl Register
    124
    
    Rxdescqueuehighaddress Register
    124
    
    Rxdescqueue1Ptrs Register
    125
    
    Rxdescqueue2Lowaddress Register
    125
    
    Rxdescqueue2Ptrs Register
    126
    
    Rxdmastatus Register
    126
    
    Rxaddressfilteringctrl Register
    128
    
    Rxframetestout Register
    130
  - PCI Diagnostic Registers
    131
  - Pcitargetstatus Register
    131
  - Pcimasterstatus1 Register
    132
  - Pcimasterstatus2 Register
    133
  - PCI Dmalowhostaddress Register
    133
  - Bacdmadiagnostic1 Register
    134
  - Bacdmadiagnostic2 Register
    135
  - Bacdmadiagnostic3 Register
    136
  - Macaddr1 Register
    137
  - Macaddr2 Register
    137
  - PCI Cardbus Registers
    138
  - Functionevent Register
    138
  - Functioneventmask Register
    139
  - Functionpresentstate Register
    139
  - Forcefunction Register
    140
  - Additional Ethernet Registers
    141
    
    Ethernet Physical Device Registers
    141
    
    Miiregistersaccessport Register
    141
    
    Rx General Frame Processor Control Register
    142
    
    Testmode Register
    142
    
    Txframeprocessorctrl Register
    142
    
    MAC Control Registers
    143
    
    Macconfig1 Register
    143
    
    Macconfig2 Register
    145
    
    Bktobkipg Register
    146
    
    Colretry Register
    147
    
    Nonbktobkipg Register
    147
    
    Maxlength Register
    148
    
    Txbytecnt Register
    148
    
    Txnibblecnt Register
    148
    
    Retxcnt Register
    149
7-101 Mskrandomnum Register7-78

150
7-100 Randomnumgen Register7-77

150
- Randomnumgen Register
  150
- Mskrandomnum Register
  150
- Totaltxcnt Register
  150
7-104 Txpausetimer Register7-79

151
7-103 Rxbytecnt Register7-79

151
7-102

151
- Rxbytecnt Register
  151
- Txpausetimer Register
  151
- Vlantype Register
  151
7-105 Vlantype Register7-79

152
- Miistatus Register
  152
7-107 External PHY Address Examples7-81

154
7-106

154
- Address Filtering Registers
  154
- Address Filtering Memory
  154
7-108 Address Filtering Memory7-82

156
- MAC Statistic Registers
  156
- MAC Statistic Register
  156
7-110 Transmit Frame Processor Register7-87

159
7-109 MAC Statistic Register7-84

159
- Transmit Frame Processor Register
  159
- Receive Frame Processor Register
  159
Sample Driver

161
- Code Conventions
  161
- Producer-Consumer Model for the AIC-6915
  162
- Basic Register Initialization and Reset Sequence
  163
- PCI Command Register
  164
- Generalethernetctrl Register
  164
- Receive Process
  167
  - Receive Completion Descriptor Queue
    167
    
    Receive Completion Descriptor Types
    167
    
    Rxcompletionqueue1Ctrl Register
    167
  - Receive Buffer Descriptor Queue
    168
    
    Receive Buffer Descriptor Types
    168
  - Two Receive Queues
    169
  - Receive Producer/Consumer Model
    169
  - Receive Polling Model
    169
  - Receive Initialization
    169
  - Receive Interrupt Handling
    175
- Transmit Process
  176
  - Transmit Completion Descriptor Queue
    176
    
    Transmit Completion Descriptor Types
    177
  - Transmit Buffer Descriptor Queue
    177
    
    Transmit Buffer Descriptor Types
    178
  - Two Transmit Queues
    180
  - Transmit Producer-Consumer Model
    180
  - Transmit Initialization
    181
  - Transmit Handling
    185
  - Transmit Completion Interrupt Handling
    187
7-112 Fifoaccess Register7-87

189
7-111 Receive Frame Processor Register7-87

189
- AIC-6915 DDK Features
  189
  - DDK Development Environment
    190

Adaptec Categories

Adapter Computer Hardware Controller Host Adapter Software

More Adaptec Manuals

Adaptec 1737100 - 62044 SGL ENET PCI 4CH Manuals

Adaptec 1737100 - 62044 SGL ENET PCI 4CH Programmer's Manual (190 pages)

Table of Contents

Introduction

AIC-6915 Block Diagram

Receive Architecture

The AIC-6915 Receive Data Structures

2-2 Receive Buffer Descriptor (One-Size Buffer, 64-Bit Addressing)2-4

2-1 Receive Buffer Descriptor (One-Size, 32-Bit Addressing)2-4

Transmit Architecture

Transmit Host Communication Data Structure

2-10 Receive Completion Descriptor (Word 3)2-9

2-9 Receive Completion Descriptor (Word 2)2-9

PCI Module Architecture

PCI Block Diagram

Frame Processor Architecture

4-2 64-Bit PCI Reset Timing4-5

Data Processing Unit

AIC-6915 Internal Registers Summary

Register Descriptions

AIC-6915 PCI Address Map

7-101 Mskrandomnum Register7-78

7-100 Randomnumgen Register7-77

7-104 Txpausetimer Register7-79

7-103 Rxbytecnt Register7-79

7-102

7-105 Vlantype Register7-79

7-107 External PHY Address Examples7-81

7-106

7-108 Address Filtering Memory7-82

7-110 Transmit Frame Processor Register7-87

7-109 MAC Statistic Register7-84

Sample Driver

7-112 Fifoaccess Register7-87

7-111 Receive Frame Processor Register7-87

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