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1-4.
Circuit Description
HDVF-L750/HDVF-L770 consists of the following boards.
• PR-332 board
• CN-3713 board
• CN-3715 board
• SW-1636 board
• SW-1637/SW-1638 boards (HDVF-L770 only)
• VR-352 board
1-4-1.
PR-332 Board
The PR-332 board mainly consists of a power supply block, a video input block, a video signal processing circuit, a
tally control circuit, and a microcomputer.
Video Input Block
This unit has three inputs: analog (20p) interface, digital (26p) interface, and 3G SDI input.
• Analog (20p) interface
Analog HD Y/Pb/Pr signals that are input to CN100 are transferred to the video amplifier (IC204, IC205, IC206)
and the LPF (IC207), are converted to 10-bit digital signals at a rate of 74 Mbps by the A/D converter (IC300), and
are then input to the FPGA (IC1).
The HD/VD synchronizing signal generated in the sync separator IC (IC209) is input to the FPGA (IC1).
• Digital (26p) interface
LVDS signals encoded on the camera side are input to the FPGA (IC1) through CN101, and are then decoded to
digital video signal, synchronizing signal, serial control signal, and TALLY lighting control signal, etc.
• SDI input
The SDI signal that is input to CN501 is input to the SDI equalizer (IC501) in which impedance conversion and
level adjustment are performed. Then the processed SDI signal is input to the FPGA (IC1).
Video Signal Processing Circuit
Peaking processing, ZEBRA/FALSE COLOR processing, and WFM signal creation are applied to digital video signals
that are input to the FPGA (IC1). Then the signals are distributed to two channels, and are then input to the image
processing IC (IC2). This image processing IC (IC2) performs picture size conversion and IP conversion to convert the
input YC digital signals to full-HD YC digital signals. This IC also performs processing to combine two screens.
The full-HD YC digital signals that are output from the image processing IC (IC2) are input again to the FPGA (IC1)
that performs YC-to-RGB conversion, brightness setting, knee correction, and convolution of the guide frame and the
OSD signal. The converted and processed signals are input to the LVDS transmitter circuit (IC1400).
The LVDS transmitter converts each 8-bit RGB digital signal and synchronizing signal to LVDS signals, and outputs
the converted signals to CN1400.
The FPGA (IC1) configures a PLL circuit with the phase comparator (IC1300), VCO1, and VCO2 to control the VCO's
oscillation frequency to synchronize it with the HD signal that is input to the FPGA (IC1).
Generating Internal Test Signals
The FPGA (IC1) has two circuits to generate internal test signals at the front and rear to switch test signals and main-
line signals.
HDVF-L750/HDVF-L770
1-5
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