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6. CIRCUIT DIAGRAM
< 1-1-1-4_ANT_WCDMA_NO_DRX >
ANT1 (GSM Quad / WCDMA B1, B2, B4, B5, B8)
Rev.C
C1133
DNI
C1107
100p
SW1100
C1100
2.7n
ANT
COMMON
1
G3
G4
DNI
DNI
3
4
L1122
L1104
L5
Rev.D
2.7n
27n
1p
Rev.D
C1108
DUAL-BAND
WTR_PRX_LB_2_IN
TRI-BAND B1/2/8
B1/2/5
B2/4/5
< 1-1-4-5 TRX_WCDMA_B1_B2_B5_B8 DUAL >
TRX B1_B2
C1607
TX_MODULE_TRX_1
DNI
C1608
TRX B5(G850 RX)_B8(G900 RX)
C1619
TX_MODULE_TRX_4
DNI
C1620
LGE Internal Use Only
C1101
2.2n
2
C1102
100p
DNI
+VPWR
TX_MODULE_TRX_1
942.5MHz
FL1101
33p
C1109
12n
4
1
C1110
22p
C1111
6.8n
OUT
IN
G3
G2
G1
DNI
5
3
2
1
TX_MODULE_TRX_4
GND
CHANGE PART
2
Rev.1.0
SPDT_SEL
C1137
100p
R1104
0
WTR_TX1_OUT
BAND
SAW(FL1101)
ANT0_SW_SEL_0
ANT0_SW_SEL_1
G850
EAM62732801
G900
EAM62732901
can be removed (QMC Review)
if your TxM GSM PA gain is not much greater than SKY77573 GSM PA gain. Can remove
+VPWR
W-BAND
DPX(FL1600)
Place matching components near WTR
EAM62711201
B1
B2
EAM62810601
C1606
4.7n
WTR_PRX_MB_1_IN
C1609
2.2n
C1610
DNI
WTR_PRX_MB_2_IN
FL1600
2.2n
6
1
0.5p
ANT
RX
3
2.7n
TX
Shunt cap must be<=33pF
guarantee LNA gain setting time
2
9
GND1
GND6
4
8
GND2
GND5
5
7
C1611 100p
C1612
L1600
GND3
GND4
DC block needed only if using MuRata B2 duplexer
Place matching components near WTR
FL1601
2.2n
C1621 100p
B5(G850), B8(G900)
6
1
C1622
5.6n
WTR_PRX_LB_1_IN
ANT
RX
3
8.2n
DNI
TX
2
9
GND1
GND6
4
8
Shunt cap must be<=33pF
GND2
GND5
5
7
guarantee LNA gain setting time
GND3
GND4
L1604
C1623 100p
C1624
2.7n
DNI
W-BAND
DPX(FL1601)
B5
EAM62671701
B8
EAM62711101
0628 change : EAM62811301_MURATA -> EAM62792801_WISOL
C1103
2.2n
1842.50MHz/1960.00MHz
RX_G1800
GSM1800_OUT
6
RX_G1900
C1104
2.7n
GND5
7
GND6
8
GSM1900_OUT
9
GND15
GND10
22
12
GND16
GND9
23
11
TRX1
GND8
24
10
GND17
GND7
25
9
TRX2
GND6
26
SKY77573-31
8
GND18
GND5
27
7
U1100
TRX3
GND4
28
6
+VPWR
GND19
VCC2
29
5
TRX4
VCC1
30
4
GND20
GND3
31
3
VBATT
GND2
32
2
NC1
GND1
33
1
PA0_R_1
PA0_R_0
ANT0_SW_SEL_3
ANT0_SW_SEL_2
Rev 0.4
Place matching components near WTR
B1
+VPWR
B2
U1600
13
2
GND5
RFIN
12
SKY77742-21
3
VCC
VENHB
PA0_ON_0
11
4
GND4
VENLB
PA0_ON_2
6.8p
10
5
RFOUTLB
VMODE
PA0_R_0
WTR_PDET_IN
PA LOGIC B1/B2/B5/B8
POWER MODE
PA0_ON_0
PA0_ON_2
PA0_R_0
SHUT DOWN
L
L
L
STAND-BY
L
L
-
B1 B2 LPM
H
L
H
B1 B2 HPM
H
L
L
B5 B8 LPM
L
H
H
B5 B8 HPM
L
H
L
- 183 -
GND3
4
Place matching components near WTR
GND2
3
GND1
2
L1105
3.3n
L1106
2.2n
WTR_PRX_MB_3_IN
GSM1800/1900_IN
1
G1800, G1900
DNI
2
1
TXM LOGIC(SPDT OFF)
SPDT_SEL
ANT0_SW_SEL0
ANT0_SW_SEL1
ANT0_SW_SEL2
LB_HPM
L
L
H
LB_MPM
L
L
H
LB_LPM
L
L
H
LB_ULPM
L
L
H
HB_HPM
L
H
L
HB_MPM
L
H
L
HB_LPM
L
H
L
HB_ULPM
L
H
L
TRX1
H
L
L
TRX2
H
L
L
TRX3
H
L
H
TRX4
H
L
H
RX1
H
H
H
RX2
H
H
H
R1604
R1605
R1606
R1607
Rev.D
0817_ADDED_Band indicate
C1613
100p
B1, B2, B5, B8
WTR_TX3_OUT
PAM THERM
Place thermistor near PAs
+1V8_VREG_L8
0530 add
2
R1602
100K
1%
1
PT1600
PA_THERM_0
0530 add
2
100K
R1603
220K
C1626
DNI
1%
1
TOL=0.01
6. CIRCUIT DIAGRAM
ANT0_SW_SEL3
PA0_R0
PA0_R1
L
L
L
L
L
L
L
H
L
L
H
L
L
L
H
H
L
L
L
L
L
L
L
H
L
L
H
L
L
L
H
H
L
L
-
-
H
L
-
-
L
L
-
-
H
L
-
-
H
L
-
-
-
H
H
-
NONE : B1 & B5
DNI
R1604 : B1 & B8
DNI
R1605 : B2 & B5
DNI
R1604 & R1605 : B2 & B8
DNI
Open : SAFO0000501
Short : SAFP0000501
LAYER_ALIGN
DLA_1
DLA_1
DLA_2
DLA_7
DLA_7
DLA_2
DLA_3
DLA_6
DLA_3
DLA_6
DLA_4
DLA_5
DLA_4
DLA_5
Copyright © 2014 LG Electronics. Inc. All right reserved.
Only for training and service purposes
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