Texas Instruments TMS380C26 User Manual
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Texas Instruments TMS380C26 User Manual

Texas Instruments TMS380C26 User Manual

Network commprocessor
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IEEE 802.5 and IBM Token-Ring Network
Compatible
IEEE 802.3 and Blue Book Ethernet
Network Compatible
Pin and Software Compatible With the
TMS380C16
Configurable Network Type and Speed:
– Selectable by Host Software Control
(Adapter Control Register)
– Selectable by Network Front-End
– Readable from Host (Adapter Control
Register)
Token-Ring Features
– 16- or 4-Megabit-per-Second Data Rates
– Supports up to 18K-Byte Frame Size
(16 Mbps Operation Only)
– Supports Universal and Local Network
Addressing
– Early Token Release Option (16 Mbps
Operation Only)
– Compatible With the TMS38054
Ethernet Features
– 10-Megabit-per-Second Data Rate
– Compatible With Most Ethernet Serial
Network Interface Devices
– Full Duplex Ethernet Operation Allows
Network Speed Self-test
Expandable Local LAN Subsystem Memory
Space up to 2 Megabytes
Supports Multicast Addressing of Network
Group Addresses Through Hashing
Glueless Interface to DRAMs
High-Performance 16-Bit CPU for
Communications Protocol Processing
Up to 8 Megabyte-per-Second High-Speed
Bus Master DMA Interface
network commprocessor applications diagram
Attached
System
Bus
PRODUCTION DATA information is current as of publication date.
Products conform to specifications per the terms of Texas Instruments
standard warranty. Production processing does not necessarily include
testing of all parameters.
Low-Cost Host-Slave I/O Interface Option
Up to 32-Bit Host Address Bus
Selectable Host System Bus Options
80x8x or 68xxx-Type Bus and Memory
Organization
– 8- or 16-Bit Data Bus on 80x8x Buses
– Optional Parity Checking
Dual-Port DMA and Direct I/O Transfers to
Host Bus
Specification for External Adapter-Bus
Devices (SEADs) Supports External
Hardware Interface for User-Defined
External Logic
Enhanced Address Copy Option (EACO)
Interface Supports External Address
Checking Logic for Bridging or External
Custom Applications
Support for Module High-Impedance
In-Circuit Testing
Built-in Real-Time Error Detection
Bring-Up and Self-Test Diagnostics With
Loopback
Automatic Frame Buffer Management
Slow-Clock Low-Power Mode
Single 5-V Supply
1- m CMOS Technology
250 mA Typical Latch-Up Immunity at 25 C
ESD Protection Exceeds 2,000 V
132-Pin JEDEC Plastic Quad Flat Package
(PQ Suffix)
Operating Temperature Range
0 C to 70 C
LAN Subsystem
Token Ring or
Ethernet Physical
TMS380C26
Layer Circuitry
Memory
POST OFFICE BOX 1443
HOUSTON, TEXAS
77251–1443
TMS380C26
NETWORK COMMPROCESSOR
SPWS010A–APRIL 1992–REVISED MARCH 1993
Transmit
To
Network
Receive
Copyright
1993, Texas Instruments Incorporated
1

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  • Page 1 Copyright 1993, Texas Instruments Incorporated PRODUCTION DATA information is current as of publication date. Products conform to specifications per the terms of Texas Instruments standard warranty. Production processing does not necessarily include testing of all parameters. POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443...

  • Page 2: Table Of Contents

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 pinout The pin assignments for TMS380C26 (132-pin quad flat-pack) are shown in Figure 1. 132-PIN QUAD FLAT PACK (TOP VIEW) V DDL V SSC CLKDIV MRAS V SSC NSELOUT0 MCAS PRTYEN MAX2 BTSTRP...
  • Page 3 Memory Interface (MIF), Protocol Handler (PH), Clock Generator (CG), and the Adapter Support Function (ASF) as shown in Figure 2. The TMS380C26 is available in a 132-pin JEDEC plastic quad flat pack and is rated from 0 C to 70 C. IBM is a registered trademark of International Business Machines Corporation.
  • Page 4 TMS380C26 has a bus interface to the host system, a bus interface to local memory, and an interface to the physical layer circuitry. As a rule of thumb in the pin nomenclature and descriptions that follow, pin names starting with the letter S attach to the host system bus and pin names starting with the letter M attach to the local memory bus.
  • Page 5 SRESET pin is asserted or the ARESET bit in the SIFACL register is set) to form a default value. This bit indicates whether chapters 0 and 31 of the memory map are RAM or ROM. If these chapters are RAM then the TMS380C26 is denied access to the local memory bus until the CPHALT bit in the BTSTRP SIFACL register is cleared.
  • Page 6 Data Direction. This signal is used as a direction control for bidirectional bus drivers. The signal becomes valid before MBEN active. MDDIR H = TMS380C26 memory bus write. L = TMS380C26 memory bus read. NOTE 4: Each pin must be individually tied to V CC with a 1.0-k pullup resistor.
  • Page 7 L = Local memory write cycle. Non-Maskable Interrupt Request. This pin must be left unconnected. External Oscillator Input. This line provides the clock frequency to the TMS380C26 for a 4-MHz OSCIN internal bus. OSCIN should be 64 a MHz signal (see Note 5).
  • Page 8 L = Local memory data bus NOT checked for parity. Network Selection Outputs. These output signals are controlled by the host through the corresponding bits of the SIFACTL register. The value of these bits/signals can only be changed while the TMS380C26 is reset. NSELOUT0 NSELOUT0...
  • Page 9 L = System Byte High enabled. System Bus Release. This pin indicates to the TMS380C26 that a higher-priority device requires the system bus. The value on this pin is ignored when the TMS380C26 is NOT perfoming DMA. This signal is internally synchronized to SBCLK.
  • Page 10 During DIO writes and DMA reads, SDDIR is low (data direction input to the TMS380C26). During DIO reads and DMA writes, SDDIR is high (data direction output from the TMS380C26). When the system interface is NOT involved in a DIO or DMA operation, then SDDIR is high by default.
  • Page 11 This signal is asynchonous, but during DMA and pseudo-DMA cycles it is internally synchronized to SBCLK. During DMA cycles, it must be asserted before the falling edge of SBCLK in state T2 in order to prevent a wait state. This signal is an output when the TMS380C26 SRDY/SDTACK is selected for DIO, and an input otherwise.
  • Page 12 System 8/16-bit bus select. This pin selects the bus width used for communications through the system interface. On the rising edge of SRESET, the TMS380C26 latches the DMA bus width; otherwise the value on this pin dynamically selects the DIO bus width.
  • Page 13 L = Write Cycle System Bus Release. This pin indicates to the TMS380C26 that a higher-priority device requires the system bus. The value on this pin is ignored when the TMS380C26 is NOT perfoming DMA. This signal is internally synchronized to SBCLK.
  • Page 14 During DIO writes and DMA reads, SDDIR is low (data direction input to the TMS380C26). During DIO reads and DMA writes, SDDIR is high (data direction output from the TMS380C26). When the system interface is NOT involved in a DIO or DMA operation, then SDDIR SDDIR is high by default.
  • Page 15 L = Data transfer is complete; system bus is ready. System Reset. This input is activated to place the adapter into a known initial state. Hardware reset will put most of the TMS380C26 output pins into a high-impedance state and place all blocks into the reset state.
  • Page 16 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 Terminal Functions (continued) Network Media Interface – Token-Ring Mode (TEST1 = H, TEST2 = H) PIN NAME DESCRIPTION DRVR Differential Driver Data Output. These pins are the differential outputs that send the TMS380C16 DRVR transmit data to the TMS38054 for driving onto the ring transmit signal pair.
  • Page 17 Ethernet Collision Detect. This input signal indicates to the TMS380C26 that the Ethernet physical layer circuitry has detected a network collision. This signal must be present for at least two TXC clock cycles to ensure it is accepted by the TMS380C26. It is normally connected to the COLL pin of an WFLT/COLL Ethernet SNI chip.
  • Page 18 External Fail-to-Match signal. An enhanced address copy option (EACO) device uses this signal to indicate to the TMS380C26 that it should not copy the frame nor set the ARI/FCI in bits in a token ring frame due to an external address match.The ARI/FCI bits in a token ring frame may be set due to an internal address matched frame.
  • Page 19 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 Terminal Functions (continued) PIN NAME DESCRIPTION V SSL Ground reference for digital logic. All V SS pins must be attached to the common system ground plane. V SS1 V SS2 V SS3 Ground connections for output buffers. All V SS pins must be attached to system ground plane.
  • Page 20 (parity or bus). Bus retries are also supported. The system interface hardware also includes features to enhance the integrity of the TMS380C26 and the data. These features do the following: Always internally maintain odd byte parity regardless if parity is disabled, Monitor for the presence of a clock failure.
  • Page 21 TMS380C26 is placed in slow clock mode. When the TMS380C26 enters the slow clock mode, the clock that failed is replaced by a slow free-running clock and the device is placed into a low-power reset state. When the failed clock(s) return to valid operation, the TMS380C26 must be re-initialized.
  • Page 22 This block also generates the reference clock to be sampled by the SIF to determine if the TMS380C26 needs to be placed into slow clock mode. This reference clock is free floating in the range of 10 – 100 kHz.
  • Page 23 Pointer to 4-/16-Mbps word flag. If zero, then 4 Mbps. If nonzero, then the adapter is set to run at 16-Mbps data rate. >01.0A0E Pointer to total TMS380C26 RAM found in Kbytes in RAM allocation test in chapter 1. † This table describes the pointers for release 1.00 and 2.x of the TMS380C26 software.
  • Page 24 Pointer to 4-/16-Mbps word flag. If zero, then 4 Mbps. If nonzero, then the adapter is set to run at 16-Mbps data rate. >01.0A0E Pointer to total TMS380C26 RAM found in Kbytes in RAM allocation test in chapter 1. † This table describes the pointers for release 1.00 and 2.x of the TMS380C26 software.
  • Page 25 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 User-Access Hardware Registers † 808x 16-Bit Mode: (SI/M = 1, S8/SHALT = 0) Normal Mode Pseudo-DMA Mode Active Word Transfers SBHE = 0 SBHE = 0 SRS2 = 0 SRS2 = 0 SBHE = 0...
  • Page 26 This bit contains the current value of the pseudo-DMA direction. This enables the host to easily determine the direction of DMA transfers, which allows system DMA to be controlled by system software. Pseudo-DMA from host system to TMS380C26. Pseudo-DMA from TMS380C26 to host system. POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443...
  • Page 27 ARESET — Adapter Reset This bit is a hardware reset of the TMS380C26. This bit has the same effect as the SRESET pin, except that the DIO interface to the SIFACL register is maintained. This bit will be set to one if a clock failure is detected (OSCIN, PXTALIN, RCLK, or SBCLK not valid).
  • Page 28 This bit allows the host processor to enable or disable system interrupt requests from the TMS380C26. The system interrupt request from the TMS380C26 is on the SINTR/SIRQ pin. The following equation shows how the SINTR/SIRQ pin is driven. The table also explains the results of the states.
  • Page 29 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 SIFACL Control for Pseudo-DMA Operation Pseudo-DMA is software controlled by the use of five bits in the SIFACL register. The logic model for the SIFACL register control of pseudo-DMA operation is shown in Figure 3.
  • Page 30 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 † absolute maximum ratings over operating free-air temperature range (unless otherwise noted) Supply voltage range, V (see Note 6) ............
  • Page 31 2 V (High) 0.8 V (Low) test measurement The test load circuit shown in Figure 4 represents the programmable load of the tester pin electronics which are used to verify timing parameters of TMS380C26 output signals. Tester Pin I OL Electronics...

  • Page 32: Clkdiv

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION Reference 4 Periods 8 Periods 12 Periods 16 Periods 20 Periods OSCIN When CLKDIV = 1 OSCOUT MBCLK1 † MBCLK2 † † The MBCLK1 and MBCLK2 signals have no timing relationship to the OSCOUT signal. The MBCLK1 and MBCLK2 signals can start on any OSCIN rising edge, depending on when the memory cycle starts execution.

  • Page 33: Prtyen

    PARAMETER MEASUREMENT INFORMATION timing parameters The timing parameters for all the pins of TMS380C26 are shown in the following tables and are illustrated in the accompanying figures. The purpose of these figures and tables is to quantify the timing relationships among the various signals.
  • Page 34 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION power up, SBCLK, OSCIN, MBCLK1, MBCLK2, SYNCIN, and SRESET timing PARAMETER UNIT 100 † t r(VDD ) Rise time from 1.2 V to V DD minimum high level 101 †‡...
  • Page 35 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION Minimun V DD High Level V DD SBCLK OSCIN MBCLK1 MBCLK2 SRESET S8/SHALT NOTE A: In order to represent the information on one figure, non-actual phase and timebase characteristics are shown. Please refer to specified parameters for precise information.
  • Page 36 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION memory bus timing: clocks, MAL, MROMEN, MBIAEN, NMI, MRESET, and ADDRESS is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) PARAMETER UNIT Period of MBCLK1 and MBCLK2...
  • Page 37 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION MBCLK1 MBCLK2 MAX0, MAX2, ADD/EN Address MROMEN MAXPH, MAXPL, MADL0–MADL7 Address Status MADH0–MADH7 Valid MRESET Valid Figure 7. Memory Bus Timing: Clocks, MAL, MROMEN, MBIAEN, NMI, MRESET, and ADDRESS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443...
  • Page 38 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION memory bus timing: clocks, MRAS, MCAS, and MAL to ADDRESS is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) PARAMETER UNIT Setup time of row address on MADL0–MADL7, MAXPH, and MAXPL before MRAS no longer 1.5t M –...
  • Page 39 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION MAXPH, Column Column MAXPL, MADL0–MADL7 MRAS MCAS MAX0, ADD/EN Address MAX2, MROMEN Address Status Address Status MADH0–MADH7 Figure 8. Memory Bus Timing: Clocks, MRAS, MCAS, and MAL to ADDRESS POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443...
  • Page 40 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION memory bus timing: read cycle is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) PARAMETER UNIT Access time from address/enable valid on MAX0, MAX2, and MROMEN to valid data/parity 6t M –...
  • Page 41 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION MAX0, Address/ MAX2, Address Enable MROMEN Data/Parity MAXPH, MAXPL, Address/ Address Address MADH0–MADH7, Status MADL0–MADL7 MRAS MCAS MBIAEN MBEN MDDIR Figure 9. Memory Bus Timing: Read Cycle POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443...
  • Page 42 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION memory bus timing: write cycle is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) PARAMETER UNIT Setup time of MW low before MRAS no longer low 1.5t M –...
  • Page 43 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION MAX0, Address/ Address MAX2, Enable MROMEN MAXPH, MAXPL, Address ADD/STS Data/Parity Out MADH0–MADH7, MADL0–MADL7 MRAS MCAS MBEN MDDIR Figure 10. Memory Bus Timing: Write Cycle POST OFFICE BOX 1443 HOUSTON, TEXAS...
  • Page 44 Hold time of MBRQ low after MBCLK1 low, bus release Setup time of MBGR low before MBCLK1 rising edge, bus release MBCLK1 MAX0, MAX2, MROMEN MAXPH, MAXPL, MADH0–MADH7, MADL0–MADL7 MRAS MCAS Figure 11. Memory Bus Timing: TMS380C26 Releases Control of Bus POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443...
  • Page 45 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION MBCLK1 MBCLK2 MBEN MDDIR MBIAEN MBRQ MBGR Figure 12. Memory Bus Timing: TMS380C26 Releases Control of Bus (continued) POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443...
  • Page 46 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION memory bus timing: TMS380C26 resumes control of bus is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) PARAMETER UNIT Hold time of MIF output high impedance after MBCKL1 rising edge, bus resume t M –...
  • Page 47 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION MBCLK1 MAX0, MAX2, MOROMEN MAXPH, MAXPL, MADH0–MADH7, MADL0–MADL7 MRAS MCAS Figure 13. Memory Bus Timing: TMS380C26 Resumes Control of Bus POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443...
  • Page 48 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION MBCLK1 MBCLK2 MBEN MDDIR MBIAEN MBRQ MBGR Figure 14. Memory Bus Timing: TMS380C26 Resumes Control of Bus (continued) POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443...
  • Page 49 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION memory bus timing: external bus master read from TMS380C26 is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) PARAMETER UNIT Setup time of address on MAX0 and MAX2 before MBCLK1 falling edge, external bus master access...
  • Page 50 PARAMETER MEASUREMENT INFORMATION MBCLK1 MBCLK2 Address In Address In MAX0, MAX2 MAXPH, MAXPL, Data/Parity MADH0–MADH7, MADL0–MADL7 Address In Address In MDDIR MACS Figure 15. Memory Bus Timing: External Bus Master Read From TMS380C26 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443...
  • Page 51 Hold time of MDDIR high after MBCLK2 low, external bus master write MBCLK1 Address In Address In MAX0, MAX2 MAXPH, MAXPL, Data/Pty MADH0–MADH7, MADL0–MADL7 Address In Address In MDDIR MACS Figure 16. Memory Bus Timing: External Bus Master Write To TMS380C26 POST OFFICE BOX 1443 HOUSTON, TEXAS 77251–1443...
  • Page 52 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION memory bus timing: DRAM refresh timing is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) PARAMETER UNIT Setup time of row address on MADL0–MADL7, MAXPH, and MAXPL before MRAS no longer 1.5t M –11.5...
  • Page 53 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION XMATCH and XFAIL timing is the cycle time of one-eighth of a local memory cycle (31.25 ns minimum) PARAMETER UNIT Delay from status bit 7 high to XMATCH and XFAIL recognized...
  • Page 54 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION token ring — ring interface timing PARAMETER UNIT 4Mbps Period of RCLK (see Note 14) Period of RCLK (see Note 14) 16 Mbps 31.25 4 Mbps nominal: 62.5 ns 154L...
  • Page 55 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION token ring — transmitter timing (see Figure 20) PARAMETER TYP MAX UNIT Delay from DRVR rising edge (1.8 V) to DRVR falling edge (1.0 V) or DRVR falling edge (1.0 V) to DRVR rising edge (1.8 V)
  • Page 56 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION ethernet timing of clock signals PARAMETER UNIT CLKPHS Pulse duration of TXC CLKPER Cycle time of TXC 1000 2.4 V 0.45 V Figure 21. Ethernet Timing Of Clock Signals ethernet timing of XMIT signals...
  • Page 57 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION ethernet timing of RCV signals — start of frame PARAMETER UNIT RXDSET Setup of RXD before RXC no longer low RXDHLD Hold of RXD after RXC high CRSSET Setup of CRS high before RXC no longer low for first valid data sample...
  • Page 58 NOTE 18: TMS380C26 will operate correctly even with no extra RXC clock cycles, providing that CRS does not remain asserted longer than 2 s (see timing spec, NDRXC). Providing no extra clocks affect receive startup timing, see timing spec, SAMDLY.
  • Page 59 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION ethernet timing of RCV signals — no RXC PARAMETER UNIT NORXC Time with no clock pulse on RXC, when CRS is high (see Note 19) NOTE 19: If NORXC is exceeded local clock failure circuitry may become activated, resetting the device.
  • Page 60 Minimum pulse duration of COLL high for guaranteed sample 20 ns + 1 cycle NOTE 20: The JAM pattern is delayed until after the completion of the preamble pattern. The TMS380C26 transmits a JAM pattern of all ”1”s. Data Data...

  • Page 61: Siack

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 80x8x DIO read timing PARAMETER UNIT Delay from SRDY low to either SCS or SRD high Pulse duration, SRAS high 259 † Hold of SAD high-impedance after SRD low (see Note 21) Setup of SADH0–SADH7, SADL0–SADL7, SPH and SPL valid before SRDY low...
  • Page 62 SPH, SPL (see Note B) † When the TMS380C26 begins to drive SDBEN inactive, it has already latched the write data internally. Parameter 263 must be met to the input of the data buffers. NOTES: A. In 80x8x mode, SRAS may be used to strobe the values of SBHE, SRSX, SRS0–SRS2, and SCS. When used to do so, SRAS must meet parameter 266a, and SBHE, SRS0–SRS2, and SCS must meet parameter 264.
  • Page 63 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 80x8x DIO write timing PARAMETER UNIT Delay from SRDY low to either SCS or SWR high Pulse duration, SRAS high Setup of SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid before SCS or SWR no longer low Hold of SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid after SCS or SWR high...
  • Page 64 SPH, SPL (see Note A) † When the TMS380C26 begins to drive SDBEN inactive, it has already latched the write data internally. Parameter 263 must be met to the input of the data buffers. NOTE A: In 8-bit 80x8x mode DIO writes, the value placed on SADH0–SADH7 is a don’t care.
  • Page 65 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 80x8x interrupt acknowledge timing – first SIACK pulse PARAMETER UNIT Pulse duration, SIACK high between DIO accesses (see Note 21) Pulse duration, SIACK low on first pulse of two pulses 62.5...
  • Page 66 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION SCS, SRSX, Only SCS needs to be inactive. SRS0–SRS2, All others are Don’t Care. SBHE SIACK 273a 272a 273a 272a 272a 273a (High) SDDIR 282R 283R SDBEN 282a SRDY †...
  • Page 67 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 80x8x mode bus arbitration timing, SIF takes control PARAMETER UNIT Setup of asynchronous signal SBBSY and SHLDA before SBCLK no longer high to guarantee 208a recognition on that cycle Hold of asynchronous signal SBBSY and SHLDA after SBCLK low to guarantee recognition on...
  • Page 68 PARAMETER MEASUREMENT INFORMATION User Master Bus Exchange SIF Master (T4) SIF Inputs: SBCLK 208a SBBSY, SHLDA 208b SIF Outputs: SHRQ SRD, SWR 241a SBHE SADH0–SADH7, Address Valid SADL0–SADL7, SPH, SPL 224c Write SDDIR Read 224a SOWN (see Note A) NOTE A: While the system interface DMA controls are active (i.e., SOWN is asserted), the SCS input is disabled. Figure 32.
  • Page 69 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 80x8x mode DMA read timing PARAMETER UNIT Setup of SADL0–SADL7, SADH0–SADH7, SPH, and SPL valid before SBCLK in T3 cycle no longer high Hold of SADL0–SADL7, SADH0–SADH7, SPH, and SPL valid after SBCLK low in T4 cycle if...
  • Page 70 PARAMETER MEASUREMENT INFORMATION TWAIT SBCLK HI-Z SRAS SBHE Valid (see Note B) (High) 227R 223R (see Note A) SXAL 216a SALE 207a SADH0–SADH7, Address Data Address SADL0–SADL7, SPH, SPL 247 † Extended (see Note C) Address 207b 208a SRDY 225R 208b 237R SDBEN...
  • Page 71 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 80x8x mode DMA write timing PARAMETER UNIT Setup of asynchronous signal SRDY before SBCLK no longer high to guarantee recognition 208a on that cycle 208b Hold of asynchronous signal SRDY after SBCLK low to guarantee recognition on that cycle Delay from SBCLK low to SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid...
  • Page 72 PARAMETER MEASUREMENT INFORMATION TWAIT SBCLK SBHE Valid (see Note A) (HIGH) 223W 227W SXAL 216a SALE SADL0–SADH7, Address Output Data SADH0–SADL7, SPH, SPL (see Note B) Extended Address 208a SRDY 237W 225W 208b 225WH SDBEN (HIGH) SDDIR NOTES: A. In 8-bit 80x8x mode, SBHE/SRNW is a don’t care input during DIO and an inactive (high) output during DMA. B.
  • Page 73 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 80x8x mode bus arbitration timing, SIF returns control PARAMETER UNIT Delay from SBCLK low in I1 cycle to SADH0–SADH7, SADL0–SADL7, SPL, SPH, SRD, and SWR 220 † high-impedance 223b †...

  • Page 74: Sbrls

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 80x8x mode bus release timing PARAMETER UNIT 208a Setup of asynchronous input SBRLS low before SBCLK no longer high to guarantee recognition 208b Hold of asynchronous input SBRLS low after SBCLK low to guarantee recognition...
  • Page 75 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 68xxx DIO read timing PARAMETER UNIT Delay from SDTACK low to either SCS, SUDS, or SLDS high 259 † Hold of SAD high-impedance after SUDS or SLDS low (see Note 21) Setup of SADH0–SADH7, SADL0–SADL7, SPH, and SPL valid before SDTACK low...
  • Page 76 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION SCS, SRSX, Valid SRS0, SRS1 SIACK 273a SRNW SUDS, SLDS SDDIR (High) 282R 283R SDBEN 282a SDTACK † HI-Z HI-Z 261a SADH0–SADH7, SADL0–SADL7, HI-Z Output Data Valid HI-Z SPH, SPL †...
  • Page 77 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 68xxx DIO write timing PARAMETER UNIT Delay from SDTACK low to either SCS, SUDS or SLDS high Setup of write data valid before SUDS or SLDS no longer low Hold of write data valid after SUDS or SLDS high 267 §...
  • Page 78 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION SCS SRSX, Valid SRS0, SRS1 SIACK 273a SRNW 272a SUDS, SLDS (see Note A) 273a 281a SDDIR (High) 282W 283W SDBEN ‡ SDTACK † HI-Z HI-Z 282b (see Note 36) SADH0–SADH7,...
  • Page 79 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 68xxx interrupt acknowledge cycle timing PARAMETER UNIT Delay from SDTACK low to either SCS or SUDS, or SIACK high 259 † Hold of SAD high-impedance after SIACK no longer high (see Note 21) Setup of output data valid before SDTACK no longer high 261 †...
  • Page 80 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION SCS, SRSX, SRS0, SRS1, Only SCS needs to be Inactive. SBHE All Others are Don’t Care. SIACK 272a SRNW 273a SLDS (High) SDDIR 282R 283R SDBEN 282a HI-Z HI-Z SDTACK †...
  • Page 81 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 68xxx mode bus arbitration timing, SIF takes control PARAMETER UNIT Setup of asynchronous input SBGR before SBCLK no longer high to guarantee recognition on 208a this cycle 208b Hold of asynchronous input SBGR after SBCLK low to guarantee recognition on this cycle...

  • Page 82: Sbbsy

    PARAMETER MEASUREMENT INFORMATION User Master Bus Exchange SIF Master (T4) SIF Inputs: SBCLK 208b 208a SBGR SBERR, SDTACK, SBBSY SIF Outputs: SBRQ (see Note A) 208a 208b SAS, SLDS, Output (Input) SUDS READ SRNW WRITE SADH0–SADH7, HI-Z SADL0–SADL7, SPH, SPL 224c WRITE SDDIR...

  • Page 83: Sxal

    TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 68xxx mode DMA read timing PARAMETER UNIT Setup of input data valid before SBCLK in T3 cycle no longer high Hold of input data valid after SBCLK low in T4 cycle if parameters 207a and 207b not met...
  • Page 84 PARAMETER MEASUREMENT INFORMATION TWAIT SBCLK (see Note A) 223R SUDS, SLDS (High) SRNW SXAL 216a SALE 233a 207a SADL0–SADH7, Address Data In HI-Z SADH0–SADL7, SPH, SPL Extended Address 247 † 207b 208a SDTACK (see Notes B and C) 208b SDDIR 225R 237R SDBEN...
  • Page 85 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 68xxx mode DMA write timing PARAMETER UNIT Setup of asynchronous input SDTACK before SBCLK no longer high to guarantee recognition 208a on this cycle 208b Hold of asynchronous input SDTACK after SBCLK low to guarantee recognition on this cycle...
  • Page 86 PARAMETER MEASUREMENT INFORMATION TWAIT SBCLK 223W 233a SUDS, SLDS 211a SRNW SXAL 216a SALE SADL0–SADH7, Address Output Data SADH0–SADL7, SPL, SPH Extended Address 208a SDTACK (see Notes A and B) 208b 225W SDDIR 225WH 237W SDBEN NOTES: A. All V SS pins should be routed to minimize inductance to system ground. B.
  • Page 87 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 68xxx mode bus arbitration timing, SIF returns control PARAMETER UNIT 220 † Delay from SBCLK low in I1 cycle to SAD, SPL, SPH, SUDS, and SLDS high-impedance, bus release 223b †...
  • Page 88 PARAMETER MEASUREMENT INFORMATION SIF Master Bus Exchange User SIF Inputs: SBCLK SBGR SDTACK SIF Outputs: SBRQ (see Note A) SAS, SUDS, SLDS 223b READ HI-Z SRNW WRITE SADH0–SADH7, HI-Z SADL0–SADL7, SPH, SPL 224d WRITE SDDIR READ 224b SOWN NOTE A: In 80x8x mode, the system interface deasserts SHRQ on the rising edge of SBCLK following the T4 state of the last system bus transfer it controls. In 68xxx mode, the system interface deasserts SBRQ on the rising edge of SBCLK in state T2 of the first system bus transfer it controls.
  • Page 89 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION 68xxx mode bus release and error timing PARAMETER UNIT 208a Setup of asynchronous input before SBCLK no longer high to guarantee recognition 208b Hold of asynchronous input SBRLS, SOWN, or SBERR after SBCLK low to guarantee recognition...
  • Page 90 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 PARAMETER MEASUREMENT INFORMATION normal completion with delayed start † T(W or 2) SBCLK SDTACK SBERR SHALT † rerun cycle with delayed start TH B TH E SBCLK SDTACK SBERR SHALT SOWN † Only the relative placement of the edges to SBCLK falling edge is shown. Actual signal edge placement may vary from waveforms shown.
  • Page 91 TMS380C26 NETWORK COMMPROCESSOR SPWS010A–APRIL 1992–REVISED MARCH 1993 MECHANICAL DATA JEDEC plastic leaded quad flat package (PQ suffix) Each of these chip carrier packages consists of a circuit mounted on a lead frame and encapsulated within an electrically nonconductive plastic compound. The compound withstands soldering temperatures with no deformation, and circuit performance characteristics remain stable when the devices are operated in high-humidity conditions.
  • Page 92 IMPORTANT NOTICE Texas Instruments and its subsidiaries (TI) reserve the right to make changes to their products or to discontinue any product or service without notice, and advise customers to obtain the latest version of relevant information to verify, before placing orders, that information being relied on is current and complete. All products are sold subject to the terms and conditions of sale supplied at the time of order acknowledgement, including those pertaining to warranty, patent infringement, and limitation of liability.

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