Texas Instruments ThunderLAN TNETE211 Programmer's Manual
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Texas Instruments ThunderLAN TNETE211 Programmer's Manual

Texas Instruments ThunderLAN TNETE211 Programmer's Manual

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ThunderLAN
TNETE100A, TNETE110A, TNETE211
Programmer's
Guide
October 1996
Network Business Products

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Summary of Contents for Texas Instruments ThunderLAN TNETE211

  • Page 1 ThunderLAN TNETE100A, TNETE110A, TNETE211 Programmer’s Guide October 1996 Network Business Products...
  • Page 2 Printed in U.S.A., October 1996 SPWU013A L411001–9761 revision A...
  • Page 4 ThunderLAN Programmer’s Guide TNETE100A, TNETE110A, TNETE211 Literature Number: SPWU013A Manufacturing Part Number: L411001-9761 revision A October 1996...
  • Page 5 Running Title—Attribute Reference IMPORTANT NOTICE Texas Instruments (TI) reserves the right to make changes to its products or to discontinue any semiconductor product or service without notice, and advises its customers to obtain the latest version of relevant information to verify, before placing orders, that the information being relied on is current.

  • Page 6: Read This First

    Preface Read This First About This Manual The ThunderLAN Programmer’s Guide assists you in using the following implementations of ThunderLAN networking hardware: TNETE100A Ethernet controller TNETE110A Ethernet controller TNETE211 100 VG-AnyLAN physical media interface (PMI) How to Use This Manual The goal of this book is to assist you in the development of drivers for the ThunderLAN controllers.
  • Page 7 Notational Conventions Notational Conventions This document uses the following conventions: Program listings, program examples, and interactive displays are shown in a special font. Examples use a bold version of the special font for emphasis. Here is a sample program listing: 11 0005 0001 .field...

  • Page 8: If You Need Assistance

    When making suggestions or reporting errors in documentation, please include the following information that is on the title page: the full title of the book, the publication date, and the literature number. Mail: Texas Instruments Incorporated Email: comments@books.sc.ti.com Technical Documentation Services, MS 702 P.O.
  • Page 9 Trademarks Trademarks Ethernet is a trademark of Xerox Corporation. ThunderLAN and Adaptive Performance Optimization are trademarks of Texas Instruments Incorporated.

  • Page 10: Table Of Contents

    Contents Contents ThunderLAN Overview ............ThunderLAN Architecture .
  • Page 11 Contents 4.4.1 No Interrupt (Invalid Code). Int_type = 000b ......4.4.2 Tx EOF Interrupt. Int_type = 001b .
  • Page 12 Contents A.1.13 PCI Memory Base Address Register (@ 14h) ......A.1.14 PCI BIOS ROM Base Address Register (@ 30h) .
  • Page 13 Contents TNETE211 100VG-AnyLAN Demand Priority Physical Media Independent (PMI) Interface B-1 100VG-AnyLAN Training ........... . TNETE211 Register Descriptions .
  • Page 14 Figures Figures 1–1 The ThunderLAN Controller ........... . 1–2 PCI Bus Byte Assignment .
  • Page 15 Tables Tables 2–1 ThunderLAN EEPROM Map ..........2-30 4–1 Adapter Check Bit Definitions...
  • Page 16 Tables A–25 ThunderLAN PHY Status Register Bits ......... . A-50 B–1 PHY Generic Control Register Bits...

  • Page 18: Thunderlan Overview

    Running Title—Attribute Reference Chapter 1 ThunderLAN Overview The ThunderLAN family consists of highly integrated, single-chip networking hardware. It uses a high-speed architecture that provides a complete peripher- al component interconnect (PCI)- to-10Base-T/AUI (adapter unit interface) Ethernet solution. It allows the flexibility to handle 100M-bps Ethernet proto- cols as the user’s networking requirements change.

  • Page 19: Thunderlan Architecture

    ThunderLAN Architecture 1.1 ThunderLAN Architecture Figure 1–1. The ThunderLAN Controller FIFO registers 802.3 PCI Bus controller controller Multiplexed SRAM 100M-bps An integrated PHY provides interface functions for 10Base-T carrier sense multiple access/collision detect (CSMA/CD) (Ethernet). A MII is used to com- municate with the integrated PHY.

  • Page 20: Networking Protocols

    Networking Protocols 1.2 Networking Protocols The MII also allows freedom in choosing a networking protocol. It allows the use of standard 100M bps CSMA/CD PHY chips. ThunderLAN uses these sig- nal lines to interface to an external 100M bps demand priority PHY. This gives ThunderLAN the flexibility necessary to handle 10Base-T, 10Base-2, 10Base-5 AUI, 100Base-TX, 100Base-T4, 100Base-FX, and 100VG-AnyLAN today, while supporting emerging technologies.

  • Page 21: Pci Interface

    PCI Interface 1.3 PCI Interface The PCI local bus is a high-performance, 32- or 64-bit bus with multiplexed ad- dress and data lines. The bus is designed to be a medium between highly inte- grated peripheral controller components such as ThunderLAN, add-in boards, and processor/memory systems.

  • Page 22: Byte Ordering

    PCI Interface 1.3.2 Byte Ordering ThunderLAN follows the PCI Local Bus Specification convention when trans- ferring data on the PCI bus. The PCI bus data is transferred on the PAD[31::0] lines. PAD31 is the most significant bit, and PAD0 is the least significant bit. The 32 data lines are enough to transfer four bytes per data cycle.

  • Page 24: Pci Configuration Space

    Chapter 2 ThunderLAN Registers ThunderLAN uses a variety of registers to perform its networking functions. These include peripheral component interface (PCI) registers, host registers, internal direct input /output (DIO) registers, media independent interface (MII) registers, and physical interface (PHY) registers. Access to these is a require- ment for setting up the ThunderLAN controller and any of the PHY devices at- tached to the MII.

  • Page 25: Bios Rom

    Register Addresses 2.1 Register Addresses The following figure shows the various register spaces provided by Thunder- LAN. It also shows how a driver uses ThunderLAN’s registers to interface to external devices such as PHYs, BIOS ROMs, and EEPROMs. Figure 2–1. How ThunderLAN Registers are Addressed ThunderLAN Host registers SRAM...
  • Page 26 Register Addresses and PCI configuration registers to make control of the system possible through the one PCI interface. An EEPROM, required by the PCI, can be written to at manufacture time through the PCI_NVRAM register, which is located in the host register space. The EEPROM can also be accessed through the NetSio register which is lo- cated in the internal/DIO register space.

  • Page 27: The Pci Configuration Space Registers

    PCI Configuration Space 2.2 PCI Configuration Space Figure 2–2. The PCI Configuration Space Registers Byte 3 Byte 2 Byte 1 Byte 0 read only Device ID Vendor ID read/write Status Command read only Base class Program interface Subclass Revision (02h) (00h) read/write Reserved...

  • Page 28: Configuration Eeprom Data Format

    PCI Configuration Space Set up the PCI bus. Several PCI bus options can be selected through these registers, including latency and grant. (Refer to PCI Local Bus Spec- ification, subsection 3.5) Map a BIOS ROM using the BIOS ROM base address register Many of the registers in the PCI configuration space are accessed with PCI BIOS calls.
  • Page 29 PCI Configuration Space Normally, access to the configuration space is limited to the operating system. On power-up, the vendor ID, device ID, revision, subclass, Min_Gnt, and Max_Lat registers are loaded with default values. Vendor-specific data is loaded into these registers by placing the data into the EEPROM, which is read at the end of reset if autoload is enabled with a pullup resistor on the EDIO pin.
  • Page 30 PCI Configuration Space r.h.ah = PCI_FUNCTION_ID; r.h.al = FIND_PCI_DEVICE; r.x.cx = DeviceID; r.x.dx = VendorID; r.x.si = Index; int86(PCI_INT, &r, &r); *pDev = (WORD)r.x.bx; return (int)r.h.ah; This code returns the function ID that is used to request reads and writes to the ThunderLAN PCI configuration space;...
  • Page 31 PCI Configuration Space r.x.di = addr; int86(PCI_INT, &r, &r); PCI_INT 0x1A */ return (r.x.cx & 0xFF); Normally, the constants in this routine (the values assigned to ah, al, and the opcode for the int86 call) are assigned in the header file for the C code. Their values are inserted as comments to enable the reader to resolve the actual val- ues that are used.

  • Page 32: Host Registers

    Host Registers 2.3 Host Registers Figure 2–4. Host Registers Base address offset HOST_CMD CH_PARM HOST_INT DIO_ADR DIO_DATA ThunderLAN implements the host registers shown above. These are the pri- mary control points for ThunderLAN. Through the host registers, a driver can: Reset the ThunderLAN controller Start transmit and receive channels Handle interrupts: Acknowledge interrupts, turn certain kinds of interrupts...
  • Page 33 Host Registers To enable reads of adjacent addresses without reposting the address, bit 15 of the DIO_ADR register can be set, which causes the address to be post-in- cremented by 4 after each access of the DIO_DATA register. This function is useful when reading the statistics or reading the internal SRAM.

  • Page 34: Internal Registers

    Internal Registers 2.4 Internal Registers Figure 2–5. Internal Registers DIO address Byte 0 Byte 3 Byte 2 Byte 1 0x00 NetCmd NetMask NetSts NetSio 0x04 Man Test NetConfig 0x08 Default Default Default Default vendor ID device ID device ID vendor ID LSbyte MSbyte LSbyte...
  • Page 35 Internal Registers Setting commit levels and PCI burst levels Interfacing via the management interface to the PHY registers Determining status interrupts Setting eight bytes of default PCI configuration data if the EEPROM checksum is bad Setting the various unicast and multicast addresses Providing network statistics Setting the LEDs and implementing a BIOS ROM The NetCmd register is used to set many of the diagnostic modes such as...
  • Page 36 Internal Registers is used to set the network transmit commit level. The BSIZEreg register is used to set the bus burst size on both Tx and Rx frames. The internal registers are accessed via the DIO_DATA and DIO_ADR host registers. DIO_ADR holds the DIO address of the register. The data is then read from or written to DIO_DATA.
  • Page 37 Internal Registers //–––––––––––––––––––––––––––––––––––––––––––––––––––––––– // DioRdDword() – read 32 bits from internal TLAN register Parameters: base_addr WORD base address of TLAN internal registers addr WORD address to read Return val: DWORD value read //–––––––––––––––––––––––––––––––––––––––––––––––––––––––– DWORD DioRdDword(WORD base_addr, WORD addr) DWORD data; addr &= 0x3fff;...

  • Page 38: Mii Phy Registers

    MII PHY Registers 2.5 MII PHY Registers Figure 2–6. MII PHY Registers Register Description Control 0x00 PHY generic control register Status 0x01 PHY generic status register PHY identifier 0x02 PHY generic identifier (high) PHY identifier 0x03 PHY generic identifier (low) AN advertisement 0x04 Autonegotiation advertisement...
  • Page 39 (AN_adv, AN_lpa, AN_exp respectively). In the vendor-specific area, Texas Instruments has implemented a TLPHY_id register. This register is used to identify ThunderLAN-specific PHY devices. ThunderLAN also implements a specific control register, TLPHY_ctl, and sta- tus register, TLPHY_sts.
  • Page 40 MII PHY Registers is 0x1F. When the internal PHY for 10Base-T is used in a standalone mode, that is, when run from another controller through the MII pins, it is at address 0x00. These are the only two addresses allowed for the internal PHY. The 100VG-AnyLAN PMI device, the TNETE211, is used to attach 802.12 physical media dependent (PMD) devices to ThunderLAN’s MII.
  • Page 41 MII PHY Registers up resistor, which is recommended to be attached to this line. The MII devices should see 1s. An alternate way to give the PHYs a series of 1s, is to: set(MDATA) set(MTXEN) clr(MCLK); //delay here DioRdByte(base_addr,Net_Sio); set(MCLK); Where MCLK is a constant for the third LSB (in the internal NetSio register) and is defined as: //delay...
  • Page 42 MII PHY Registers After synchronization, one could use code like the following to read a PHY reg- ister: //–––––––––––––––––––––––––––––––––––––––––––––––––––––––– MiiRdWord() – Read word from Phy MII, place at ptr, return status Parameters: base_addr WORD base address of TLAN internal regis- ters (passed for set/clr macros) WORD...
  • Page 43 MII PHY Registers Interrupts are turned off with the CritOn() macro. This macro leaves a value that can be sampled to see if it has been invoked. CritOn can be defined as follows: #define CritOn() if (CritLevel == 0) \ { _asm { cli } } CritLevel++ The NetSio register must be reached indirectly using the host registers.
  • Page 44 MII PHY Registers This samples data on the rising edge of the MCLK bit. Take the first bit into the PHY MII as follows: b &= ~MCLK; outp(diodata,b); b |= MDATA; outp(diodata,b); b |= MCLK; outp(diodata,b); //1 data bit out This concludes writing out the start delimiter bits.
  • Page 45 MII PHY Registers to NetSio. Then the clock is cycled for each bit. The loop effectively cycles five times. // Send the register number MSB first // Send the device number Internal=31(0x1f), External=0(0x00) for (i = 0x10;i;i >>= 1) if (i&addr) b |= MDATA;...
  • Page 46 MII PHY Registers After the addresses have been clocked out on a read cycle, there is a cycle where neither side drives the data pin. If the PHY is synced and ready to re- spond, it should drive a 0 next, followed by the 16 bits of data. The data is avail- able up to 300 ns after the rising edge of the clock, so the software loop uses that time to execute the instruction to make the clock go low again.
  • Page 47 MII PHY Registers for (i = 0;i < 17;i++) togLH(MCLK); tmp = 0xffff; //togLH b &= ~MCLK; outp(diodata,b); b |= MCLK; outp(diodata,b); b = inp(diodata); This is the quiescent cycle following data transmission. Since this is a read op- eration, ThunderLAN does not drive the line and the PHY turns off during this cycle.
  • Page 48 All bits in this register are set to 0 on the Ad_Rst bit, or when the external reset, PRST#, is activated. The meaning assigned to the LEDs, which LEDs are actually implemented, and the times to set and clear them are all programmable. Texas Instruments ThunderLAN Registers 2-25...
  • Page 49 External Devices reserves the following two LED locations for its drivers. The bit numbers refer to their locations in LEDreg. Bit 0 (LSB) displays link status. Bit 4 displays activity. 2.6.3 EEPROM The implementation-specific configuration information is read or written into the EEPROM from two sources.
  • Page 50 External Devices Writing to the NetSio register involves writing a >000 to the host register DIO_ADR, then writing to the DIO_DATA host register. Control of the EEPROM interface shifts to the bits in NetSio when a write takes place to the DIO_DATA host register.
  • Page 51 External Devices Set and clear are macros for a read/modify/write routine for individual bits in the NetSio register. The NetSio byte is read indirectly from the internal register block with the host register address and data pointers, the bit passed as a constant (really a bit mask) is ANDed to 0 (clear), or ORed to a 1 (set).
  • Page 52 External Devices When the EEPROM address is shipped out, another special pattern of control signal movements must take place to signal the start of the data transfer. // send device ID, address and read command to EEPROM sel(base_addr, READ); // EEPROM should have acked if (!ack(base_addr)) return (0);...

  • Page 53: Thunderlan Eeprom Map

    ThunderLAN EEPROM Map ThunderLAN uses the following EEPROM map. Note that these values may be used in several applications and systems including: ThunderLAN hardware A host running Texas Instruments ThunderLAN drivers Texas Instruments diagnostic routines Table 2–1. ThunderLAN EEPROM Map Address Default...
  • Page 54 External Devices Table 2–1. ThunderLAN EEPROM Map (Continued) Address Default Binary Bits Description 0x79 0x04 WxSHRAFI PHY and test control modes W – PHY wrap request S – Skip training request H – HiPriority transmit frames request R – Don’t copy short frame request A –...
  • Page 55 External Devices Table 2–1. ThunderLAN EEPROM Map (Continued) Address Default Binary Bits Description 0x82 0x00 0x83 Ethernet address 0x84 Ethernet address 0x85 Ethernet address 0x87 Ethernet address 0x88 Ethernet address 0x86 Ethernet address 0x89 0xff Checksum 0x8a 0xff Checksum 0x8b 0x83 0x8c 0x08...
  • Page 56 External Devices Table 2–1. ThunderLAN EEPROM Map (Continued) Address Default Binary Bits Description 0x9c Ethernet address 0x9d Ethernet address 0x9e Ethernet address 0x9f 0xff Checksum 0xa0 0xff Checksum 0xa1 0x83 0xa2 0x08 0xa3 0x00 0xa4 Token ring address 0xa5 Token ring address 0xa6 Token ring address 0xa7...
  • Page 57 External Devices Table 2–1. ThunderLAN EEPROM Map (Continued) Address Default Binary Bits Description 0xb6 0xff Checksum 0xb7 0xb8 0xb9 0xba 0xbb 0xbc 0xbd 0xbe 0xbf 0xc0 Vendor ID register LSbyte 0xc1 Vendor ID MSbyte 0xc2 Device ID LSbyte 0xc3 Device ID MSbyte 0xc4 Revision 0xc5...

  • Page 58: Initializing And Resetting

    Chapter 3 Initializing and Resetting This chapter describes the steps necessary to get a ThunderLAN device ready to transmit and receive frames. It provides examples of the necessary code, beginning with configuration of the ThunderLAN device on a peripheral com- ponent interconnect (PCI) system.

  • Page 59: Initializing

    Initializing 3.1 Initializing To initialize or to set the starting values for ThunderLAN, the device must pro- ceed through a specific sequence of steps. This procedure assumes that the autoconfiguration step of loading from the EEPROM to the PCI configuration registers has already taken place.
  • Page 60 Initializing WORD PciFindDevice( WORD DeviceID, WORD VendorID, WORD Index, WORD *pDev) union REGS r; r.h.ah = PCI_FUNCTION_ID; r.h.al = FIND_PCI_DEVICE; r.x.cx = DeviceID; r.x.dx = VendorID; r.x.si = Index; int86(PCI_INT, &r, &r); *pDev = (WORD)r.x.bx; return (int)r.h.ah; When the BIOS call is finished, the value returned is 0 if successful or an error code if not successful.

  • Page 61: Finding The Controller In Memory And I/O Space

    Initializing 3.1.2 Finding the Controller in Memory and I/O Space To access the host registers, the I/O base address must be determined. This I/O base is needed, since the host registers are accessed as I/O ports. The I/O base address register in the ThunderLAN controller has the LSB hardwired to high.

  • Page 62: Finding Which Interrupt Was Assigned

    Initializing 3.1.3 Finding Which Interrupt was Assigned When the base register is established, the driver needs to find out what inter- rupt was assigned to the card. The next code segment from GetPciConfig be- low retrieves the PCI_INTLINE which in x86-based PCs refers to the interrupt request (IRQ) numbers (0 –...

  • Page 63: Turning On The I/O Port And Memory Address Decode

    Initializing 3.1.4 Turning on the I/O Port and Memory Address Decode The next step in the GetPciConfig section of the code is responsible for turning on the ThunderLAN controller by enabling the decode of memory and I/O port addresses. Without this step, there is no access to the host registers and there- fore, to the internal registers or the MII granted to the host processor.

  • Page 64: Recovering The Silicon Revision Value

    Initializing 3.1.5 Recovering the Silicon Revision Value At this point, the sample program needs to know what the default silicon revi- sion for the controller is. There is a revision byte in the configuration space that can be read with a PciRdxxxx command. This configuration byte is loaded with EEPROM data to signal the board-level revision code.

  • Page 65: Resetting

    Resetting 3.2 Resetting Resetting ThunderLAN is required when conditions such as an incorrect pow- er-up cause the register value in the device to deviate from that needed for proper operation. To perform either a software or hardware reset, the program- mer must complete the steps indicated.

  • Page 66: Software Reset

    Resetting 3.2.2 Software Reset The driver needs to reset ThunderLAN at startup when an adapter check inter- rupt occurs or when an upper layer requires the driver to do so. ThunderLAN may only need to be reinitialized when link is lost. To reset ThunderLAN the driver must: 1) Clear the statistics by reading the statistics registers 2) Issue a reset command to ThunderLAN by asserting the Ad_Rst bit in the...
  • Page 67 3-10...

  • Page 68: Interrupt Handling

    Chapter 4 Interrupt Handling ThunderLAN and its host device indicate communication with each other by sending and receiving interrupts to the bus data stream. This chapter provides information on setting up code which recognizes, prioritizes, and acknowl- edges these interrupts. It defines specific interrupt codes and describes what happens when these occur.

  • Page 69: Loading And Unloading An Interrupt Service Routine (Isr)

    Loading and Unloading an Interrupt Service Routine (ISR) 4.1 Loading and Unloading an Interrupt Service Routine (ISR) Before the ThunderLAN controller can be allowed to generate an interrupt to the host, it is necessary to install code for the host to handle the interrupt. The driver also relies on other host services that are interrupt-driven, like getting notice of timer ticks for deadman timers.
  • Page 70 Loading and Unloading an Interrupt Service Routine (ISR) This routine converts either the eight low hardware interrupts, or the eight high interrupts, or a software interrupt higher than 0xF to the vector table, then makes an O/S call to get the old vector and slips in the new. It returns the pre- vious contents of that table entry so that it can be restored later.
  • Page 71 Loading and Unloading an Interrupt Service Routine (ISR) Cleanup uses the same HwSetIntVector routine to restore the old value. This time, the parameter is the old value and the interim value returned by the func- tion is ignored. Only the three interrupts that were asserted are restored, and only if the structure for the NIC instance has had old values saved in it.

  • Page 72: Prioritizing Adapter Interrupts

    Prioritizing Adapter Interrupts 4.2 Prioritizing Adapter Interrupts All (non-PCI) adapter interrupts are governed by the interrupt pacing timer. The interrupt pacing timer is started whenever the HOST_CMD register Ack bit is written as a 1. When this timer expires and if any interrupt sources are active, a PCI interrupt is asserted.

  • Page 73: Acknowledging Interrupts (Acking)

    Acknowledging Interrupts (Acking) 4.3 Acknowledging Interrupts (Acking) The ThunderLAN controllers have been designed to minimize the code neces- sary to acknowledge interrupts. This is accomplished by matching the HOST_INT register’s bits to the corresponding bits in the HOST_CMD regis- ter. Also, the HOST_INT’s two LSBs are set to 0 so that it forms a table-offset vector, which can be used in a jump table.

  • Page 74: Interrupt Type Codes

    4.4.2 Tx EOF Interrupt. Int_type = 001b Tx EOF and Tx EOC interrupt handling depends on the Tx interrupt threshold used. The interrupt threshold counter is part of Texas Instruments Adaptive Performance Optimization (APO) algorithm. More information on APO can be found in the ThunderLAN Adaptive Performance Utilization Technical Brief (TI literature number SPWT089).

  • Page 75: Statistics Overflow Interrupt. Int_Type = 010B

    Interrupt Type Codes 4.4.3 Statistics Overflow Interrupt. Int_type = 010b This interrupt is given when one of the network statistics registers is halfway filled. The driver: Reads all the statistics registers, thereby clearing them Acknowledges the interrupt, then exits When reading the statistics registers, it is a good idea to use the Adr_Inc bit in the DIO_ADR register.

  • Page 76: Tx Eoc Interrupt. Int_Type = 101B

    Interrupt Type Codes 4.4.6 Tx EOC Interrupt. Int_type = 101b A Tx EOC interrupt occurs when ThunderLAN encounters a forward pointer of 0 in the Tx list structure or when the Ld_Thr bit is loaded with 0. In this routine the driver: Gets the pointer to the Tx buffer queue Checks the list CSTAT to see if a frame has been transmitted...
  • Page 77 Interrupt Type Codes 4.4.8 Adapter Check Interrupt. Int_type = 110b and Int_Vec An adapter check interrupt occurs when ThunderLAN enters an unrecover- able state and must be reset. This unrecoverable condition occurs when ThunderLAN does not agree with the parameters given to it by the driver or when it does not agree with the external hardware.

  • Page 78: Adapter Check Interrupt Fields

    Interrupt Type Codes Figure 4–1. Adapter Check Interrupt Fields Byte 3 Byte 2 Channel Byte 1 Byte 0 Failure code Table 4–1. Adapter Check Bit Definitions Name Function 28 – 21 Channel This field indicates the active PCI channel at the time of the failure. List not data: If this bit is set to 1, a PCI list operation was in progress at the time of the failure.

  • Page 79: Adapter Check Failure Codes

    Interrupt Type Codes Table 4–2. Adapter Check Failure Codes Name Function DataPar Data parity error: Indicates that during bus master operations, ThunderLAN has de- tected a PCI bus data parity error, and parity error checking was enabled (the PAR_En bit in the PCI command register is set). AdrsPar Address parity error: Indicates that ThunderLAN has detected a PCI bus address parity error, and that parity error checking is enabled (the PAR_En bit in the PCI command...

  • Page 80: Rx Eoc Interrupt. Int_Type = 111B

    Interrupt Type Codes The error status bits are only relevant for some adapter check failure codes, as indicated by the following table: Table 4–3. Relevance of Error Status Bits for Adapter Check Failure Codes Name Channel List/Data Receive/Transmit Read/Write 01h DataPar 02h AdrsPar 03h Mabort 04h Tabort...
  • Page 81 4-14...

  • Page 82: List Structures

    Chapter 5 List Structures ThunderLAN controllers use a list processing method to move data in and out of the host’s memory. A list is a structure in host memory which is composed of pointers to data. The list contains information telling ThunderLAN where in the host memory to look for the data to be transmitted or where the receive buffer is located.

  • Page 83: List Management

    List Management 5.1 List Management Some of the more commonly used list management terms are defined here: List A list is a structure in host memory which is composed of pointers to data. The list includes information on the location of a frame, its size, and its transmission/receive status.

  • Page 84: Linked List Management Technique

    List Management can keep the transmit and receive channels continuously open by freeing up buffers and relinking lists faster than frames are transferred by ThunderLAN. This is important in receive operations where the Rx channel must be open continuously to avoid losing frames from the network. All list processing and management operations are done in host memory.
  • Page 85 List Management A driver is not limited in the number of lists it can manage as long as there is memory to put them in. The question then arises as to how many lists are ap- propriate for a certain application. The number of lists allocated should be just enough to allow the driver to use the full wire bandwidth on Tx and to handle the Rx data from the wire.

  • Page 86: Cstat Field Bit Requirements

    CSTAT Field Bit Requirements 5.2 CSTAT Field Bit Requirements Texas Instruments specifies that some bits in the CSTAT field should be set to 1, but tells you to ignore them. This is because these bits are ignored by the adapter. The ThunderLAN CSTAT is very much like that in TI380 products. Bit 12 in ThunderLAN corresponds to bit 3 in the TI380 CSTAT FRAME_END bit.

  • Page 87: One-Fragment Mode

    One-Fragment Mode 5.3 One-Fragment Mode When the GO command is given on either transmit or receive, ThunderLAN DMAs the whole list, even though the driver only uses a limited number of frag- ments on that list. In the case of a receive list, the driver has the option to force ThunderLAN to DMA a one-fragment list.

  • Page 88: Receive List Format - One_Frag

    Receive List Format 5.4 Receive List Format Figure 5–3. Receive List Format – One_Frag = 0 List offset Byte 3 Byte 2 Byte 1 Byte 0 0x00 Forward pointer 0x04 Frame size Receive CSTAT 0x08 Data count 0x0C Data address 0x10 Data count 0x14...

  • Page 89: Receive Parameter List Fields

    Receive List Format Table 5–1. Receive Parameter List Fields Field Definition Forward pointer This full 32-bit field contains a pointer to the next receive parameter list in the chain. The three LSBs of this field are ignored, as lists must always be on an eight-byte address boundary.

  • Page 90: Receive Cstat Request Fields

    Receive List Format Figure 5–5. Receive CSTAT Request Fields Table 5–2. Receive CSTAT Request Bits Name Function Ignored by adapter. Set to 0 Frm_Cmp 0 Frame complete: Ignored by adapter. Set to 0. Setting the Frm_Cmp bit to 0 is good programming practice.

  • Page 91: Receive Cstat Complete Fields

    Receive List Format Figure 5–6. Receive CSTAT Complete Fields Reserved Error Table 5–3. Receive CSTAT Complete Bits Name Function Same value as previously set by the host in CSTAT request field Frm_Cmp 1 Frame complete: Set to 1 by the adapter to indicate the frame has been received Same value as previously set by the host in CSTAT request field Same value as previously set by the host in CSTAT request field RX EOC: If RX EOC is disabled by the Interrupt Disable register no interrupts will be...

  • Page 92: Transmit List Format

    Transmit List Format 5.5 Transmit List Format Figure 5–7. Transmit List Format Byte 3 Byte 2 Byte 1 Byte 0 List offset 0x00 Forward pointer 0x04 Frame size Receive CSTAT 0x08 Data count 0x0C Data address 0x10 Data count 0x14 Data address 0x18 Data count...

  • Page 93: Transmit Parameter List Fields

    Transmit List Format Table 5–4. Transmit Parameter List Fields Field Definition Forward pointer This 32-bit field contains a pointer to the next transmit parameter list in the chain. The three LSBs of this field are ignored, as lists must always be on an eight-byte address boundary.

  • Page 94: Transmit Cstat Request Fields

    Transmit List Format Figure 5–8. Transmit CSTAT Request Fields Pass Network Reserved priority Table 5–5. Transmit CSTAT Request Bits Name Function Ignored by adapter. The value in this bit is a don’t care. Frm_Cmp 0 Frame complete: Ignored by adapter. Should be set to 0. Setting the Frm_Cmp bit to 0 is good programming practice.

  • Page 95: Transmit Cstat Complete Fields

    Transmit List Format Figure 5–9. Transmit CSTAT Complete Fields Pass Network Reserved priority Table 5–6. Transmit CSTAT Complete Bits Name Function Same value as previously set by the host in the CSTAT request field Frm_Cmp 1 Frame complete: Set to 1 by the adapter to indicate the frame has been transmitted into the controller’s internal FIFO Same value as previously set by the host in CSTAT request field Same value as previously set by the host in CSTAT request field...

  • Page 96: Transmitting And Receiving Frames

    Chapter 6 Transmitting and Receiving Frames This chapter describes the structure and format for transmitting and receiving frames using ThunderLAN. Frames are units of data that are transmitted on a network. These must appear in a consistent, logical format to be recognized. The chapter also describes the method you must use to create a linked list structure, which is necessary to start frame reception and transmission.

  • Page 97: Frame Format

    Frame Format 6.1 Frame Format The following describes the configuration of the data units which ThunderLAN transmits and receives. ThunderLAN looks for this format to create the linked structures it uses in transmitting and receiving data (see subsection 6.2, GO Command).

  • Page 98: Transmit (Tx) Frame Format

    Frame Format 6.1.2 Transmit (Tx) Frame Format The adapter transmit channels are used to transmit frames to other nodes on the network. The ThunderLAN adapter allows transmitted frame data to be fragmented into up to ten pieces. However, the adapter expects the conca- tenation of these fragments to be in a consistent, logical format as shown be- low.

  • Page 99: Go Command

    GO Command 6.2 GO Command To transmit and receive data, the ThunderLAN driver must create a linked list of frames. This subsection describes the steps to create such a linked list, and the process for initiating transfer by using a GO command. 6.2.1 Starting Frame Reception (Rx GO Command) To create a linked receive list structure the driver:...
  • Page 100 GO Command forward pointer point to the next available list. The last list should have a for- ward pointer of 0. You must then initialize the CSTAT fields in the lists. Opening a receive channel works in much the same way as opening a transmit channel.

  • Page 101: Starting Frame Transmission (Tx Go Command)

    GO Command The HOST_CMD register can be written in a single, 32-bit operation. This im- plies that several commands can be combined in one operation. An Rx EOC interrupt can be acknowledged and Rx GO commands can be reissued in a single operation.
  • Page 102 GO Command 8) Gives the TX GO command by writing the address of the first available list to the CH_PARM register 9) Writes a 1 to the GO bit of the HOST_CMD register, with the transmit chan- nel selected This assumes the transmit interrupt threshold has been initialized. If not, write to HOST_CMD with the Ld_Thr bit set and the threshold value in the Ack_Count field.
  • Page 103 GO Command Depending on the value loaded into the Ld_Thr bit in the HOST_CMD register, ThunderLAN gives a Tx EOF interrupt after processing the number of frames specified. In this case, the driver acknowledges the number of frames that it has processed.

  • Page 104: Physical Interface (Phy)

    10Base-T physical interface (PHY) and any MII-compliant networking PHYs. It also discusses IEEE 802.12-compliant devices which are supported when ThunderLAN is used in conjunction with Texas Instruments TNETE211 100VG-AnyLAN physical media independent (PMI) device. The TNETE211 implements 802.12 media access controller (MAC) state machines for 100VG- AnyLAN operation, and provides an 802.12-compatible MII.

  • Page 105: Mii-Enhanced Interrupt Event Feature

    MII-Enhanced Interrupt Event Feature 7.1 MII-Enhanced Interrupt Event Feature ThunderLAN can connect to an external PMI device through its industry stan- dard MII interface. A full description of the MII can be found in the 802.3u stan- dard. The ThunderLAN MII is enhanced in two ways: The ThunderLAN MII can be shifted through software into a mode that supports a connection to the TNETE211.

  • Page 106: Mii Frame Format: Read

    MII-Enhanced Interrupt Event Feature ThunderLAN implements the 19-signal MII shown in Table 7–1: Table 7–1. ThunderLAN MII Pins (100M-bps CSMA/CD) Name Type Function MTCLK Transmit clock: Transmit clock source from the attached PHY device MTXD0 Transmit data: Nibble transmit data from ThunderLAN. When MTXEN is asserted, MTXD1 these pins carry transmit data.

  • Page 107: Mii Frame Format: Write

    A specific PHY can be found by read- ing the PHY identifier registers (locations 0x02h and 0x03h) and matching them to a known code. For Texas Instruments PHYs and PMIs, these codes are shown below, where the xx denotes a revision: 0x4000501xx for the internal 10Base-T PHY...

  • Page 108: Possible Sources Of Mii Event Interrupts

    MII-Enhanced Interrupt Event Feature PHY interrupt function. The INTEN bit is used to enable and disable the PHY interrupt function. Setting the INTEN bit enables the PHY internal event sys- tem to generate interrupts; clearing the INTEN bit disables the PHY from gen- erating interrupts.

  • Page 109: Assertion Of Interrupt Waveform On The Mdio Line

    MII-Enhanced Interrupt Event Feature generated under host software control and is used to latch the MDIO pin on the rising edge. The ThunderLAN architecture expands the use of these two pins to allow the attached PHY to interrupt the host using ThunderLAN. The clock cycle at the end of a transaction on the MDIO signal is used to disable the PMI from driving MDIO after a register read (the quiescent cycle).

  • Page 110: Nonmanaged Mii Devices

    Nonmanaged Mll Devices 7.2 Nonmanaged MII Devices Nonmanaged MII devices do not have a management interface (MDIO and MDCLK). As such, they do not have any registers. The driver must have a key- word that denotes that the PHY used is nonmanaged. Physical Interface (PHY)

  • Page 111: Bit-Rate Devices

    Bit-Rate Devices 7.3 Bit-Rate Devices ThunderLAN supports bit-rate devices by asserting the BITrate bit in the Net- Config register. The MII is then converted into an Ethernet serial network inter- face (SNI). The pin conversion for this mode is: MRXD0 RXD (receive data) MRCLK RXC (receive clock)

  • Page 112: Phy Initialization

    PHY Initialization 7.4 PHY Initialization The driver initializes each MII-attached PHY. Since there may be more than one PHY attached to the MII, proper initialization ensures that one and only one PHY is active and driving the MII. (The condition where more than one PHY drives the MII at the same time is termed contention.) Each MII-equipped PHY device has a control register at offset 0x00h.
  • Page 113 7-10...

  • Page 114: 10Base-T Phy Registers

    Appendix A Appendix A Register Definitions This appendix contains register definitions for the TNETE100A, TNETE110A, and TNETE211 ThunderLAN implementations. ThunderLAN uses these reg- isters to store information on its internal status and its communication with the host. This appendix describes the purpose and function of each register and provides bitmaps and descriptions of individual bits.

  • Page 115: A.1 Pci Configuration Registers

    PCI Configuration Registers A.1 PCI Configuration Registers The PCI specification requires all PCI devices to support a configuration regis- ter space to allow jumperless autoconfiguration. The configuration space is 256 bytes in length, of which the first 64-byte header region is explicitly defined by the PCI standard.

  • Page 116: A.1.1 Pci Autoconfiguration From External 24C02 Serial Eeprom

    Autoconfiguration allows builders of ThunderLAN sys- tems to customize the contents of these registers to identify their own systems, rather than using the Texas Instruments defaults. The state of the EDIO pin during PCI reset (PRST#), enables (high) or disables (low) autoconfiguration.

  • Page 117: A.1.2 Pci Vendor Id Register (@ 00H) Default = 104Ch

    PCI Configuration Registers The first bit written to or read from the EEPROM is the most significant bit of the byte, such as data(7). Therefore, writing the address C0h is accomplished by writing a 1 and six 0s. ThunderLAN expects data to be stored in the EEPROM in a specific format. Nine bytes in the EEPROM are reserved for use by the adapter, starting with C0h, as shown below.

  • Page 118: A.1.4 Pci Command Register (@ 04H)

    PCI Configuration Registers Should autoconfiguration fail (bad checksum), this register is loaded with the ThunderLAN device ID of 0500h. A.1.4 PCI Command Register (@ 04h) Reserved Reserved Table A–1. PCI Command Register Bits Name Function 15 – 9 Reserved Writes to these bits are ignored; bits are always read as 0. SER_En PSERR# driver enable: A value of 1 enables the adapter PSERR# driver.

  • Page 119: A.1.5 Pci Status Register (@ 06H)

    PCI Configuration Registers A.1.5 PCI Status Register (@ 06h) DEVSEL Reserved (01b) Table A–2. PCI Status Register Bits Name Function DP_err Detected parity error: Indicates that the adapter has detected a parity error. This bit is set even if the parity error response bit is not set. This bit can only be set by the adapter, and only cleared by the host’s writing a 1 to this bit position.

  • Page 120: A.1.6 Pci Base Class Register (@ 0Bh)

    PCI Configuration Registers A.1.6 PCI Base Class Register (@ 0Bh) This register is hardwired with the network controller code of 0x02h. A.1.7 PCI Subclass Register (@ 0Ah) This register holds the adapter PCI subclass. This register is loaded from an external serial EEPROM on the falling edge of PCI reset, during autoconfi- guration.

  • Page 121: Pci Memory Base Address Register (@ 14H

    PCI Configuration Registers This register holds the base address for ThunderLAN’s register set in I/O space. Bit 0 of this register is hardwired to a 1 to indicate that this is a memory- mapped base address. Bits 1 through 3 are hardwired to 0 to indicate that the register set occupies four 32-bit words.

  • Page 122: Pci Interrupt Line Register (@ 3Ch

    PCI Configuration Registers pins. On reset (software or hardware), control of the interface is given to the PCI NVRAM register. Byte 0 NVPR Reserved DDIR DATA Reserved Reserved CDIR CLOCK Table A–3. PCI NVRAM Register Bits Name Function NVPR Nonvolatile RAM present: When this bit is set to a 1, it indicates that an external EEPROM is present.

  • Page 123: Pci Min_Gnt (@ 3Eh) And Max_Lat (@ 3Fh) Registers

    PCI Configuration Registers A.1.18 PCI Min_Gnt (@ 3Eh) and Max_Lat (@ 3Fh) Registers These byte registers are used to specify the adapter’s desired settings for la- tency timers. For both registers, the value specifies a period of time in units of 250 ns (quarter microsecond).

  • Page 124: Cardbus Cis Pointer (@ 28H

    PCI Configuration Registers A.1.20 CardBus CIS Pointer (@ 28h) This register is used by those devices that want to share silicon between Card- Bus and PCI. The field is used to point to the Card Information Structure (CIS) for the CardBus card. On ThunderLAN this register is hardwired to a value of 10000107h which indicates that the CIS information is in expansion ROM at image1 and offset 20.

  • Page 125: Adapter Host Registers

    Adapter Host Registers A.2 Adapter Host Registers Host command registers contain bits which are toggled to tell the channel to use receive or transmit FIFOs. ThunderLAN’s adapter host registers include the adapter internal registers (see section A.3, Adapter Internal Registers). The following subsections describe the functions of each host register accord- ing to protocol.
  • Page 126 Adapter Host Registers Table A–5. Host _ CMD Register Bits (Continued) Name Function Stop Channel stop: This command bit only affects the network channels. if R / T = 0 (Tx Stop): Writing a 1 to this bit stops frame transmission on all transmit channels immediately. All transmit FIFO control logic and the network transmission state machines are placed in a reset state as soon as any ongoing PCI bus transfers are complete (end of current data fragment, list, or CSTAT DMA).
  • Page 127 Adapter Host Registers Table A–5. Host _ CMD Register Bits (Continued) Name Function Interrupt acknowledge: Writing a 1 to this bit acknowledges the interrupt indicated by the Nes, EOC, Ch_Sel, and R / T fields. if Nes = 0, EOC = 1, and R / T = 1 (Status Ack): Writing a 1 to this bit acknowledges and clears the status interrupt.
  • Page 128 Adapter Host Registers Table A–5. Host _ CMD Register Bits (Continued) Name Function End of channel select: This read/write bit is used to select between the EOC, EOF, and command bit operations. If this bit is set to a 1, then end of channel operations are se- lected.
  • Page 129 Adapter Host Registers Table A–5. Host _ CMD Register Bits (Continued) Name Function Ld_Tmr Load interrupt timer : Writing a 1 to this bit causes the interrupt holdoff timer to be loaded from the Ack Count field. Ack Count indicates the time-out period in 4- s units (based on a 33-MHz PCI clock).

  • Page 130: Channel Parameter Register-Ch_Parm @ Base_Address + 4 (Host)

    Adapter Host Registers A.2.2 Channel Parameter Register–CH_PARM @ Base_Address + 4 (Host) This is used to pass parameter information for HOST_CMD register com- mands as follows: GO (Tx GO): Load CH_PARM with the address of the first transmit list be- fore issuing the command.

  • Page 131: Host Interrupt Register-Host_Int @ Base_Address + 10 (Host)

    Adapter Host Registers A.2.3 Host Interrupt Register–HOST_INT @ Base_Address + 10 (Host) Int Vec Int Type Table A–6. HOST_INT Register Bits Name Function 15 – 13 These bits are always read as 0s. 12 – 5 Int_Vec Interrupt vector: This field indicates the highest active interrupt flag for a particular inter- rupt type.

  • Page 132: Dio Address Register-Dio_Adr @ Base_Address + 8 (Host)

    Adapter Host Registers and Nes bits. This allows the value read from the interrupt register to be written to the HOST_CMD register to directly select the appropriate channel. If no in- terrupts are active, the interrupt pacing timer is running, or the PCI interrupt has been disabled (by writing a nonzero value to this register), the HOST_INT register is read as all 0s.

  • Page 133: Dio Data Register-Dio_Data @ Base_Address + 12 (Host)

    Adapter Host Registers If ADR_SEL[1::0] = 00, the 32 LSBs of the 68-bit word are accessed. If ADR_SEL[1::0] = 01, the middle 32 bits of the 68-bit word are accessed. If ADR_SEL[1::0] = 1X, the four MSBs of the 68-bit word are accessed (in the four LSBs of DIO_DATA).

  • Page 134: Adapter Internal Registers

    Adapter Internal Registers A.3 Adapter Internal Registers The adapter’s internal registers are indirectly accessible from the PCI bus through the DIO_ADR and DIO_DATA registers. These are usually referred to as DIO. ThunderLAN has an internal 32-bit bus that is used for DIO accesses to the registers and the SRAM.

  • Page 135: Adapter Internal Register Map

    Adapter Internal Registers Figure A–4. ADAPTER Internal Register Map DIO Address Byte 3 Byte 2 Byte 1 Byte 0 NetMask NetSts NetSio NetCmd 0x00 ManTest NetConfig 0x04 Default Default Default Default 0x08 device ID device ID vendor ID vendor ID MSbyte LSbyte MSbyte...

  • Page 136: Network Command Register-Netcmd @ 0X00 (Dio)

    Adapter Internal Registers A.3.1 Network Command Register–NetCmd @ 0x00 (DIO) All bits in this register are set to 0 on an Ad_Rst or when PRST# is asserted. Byte 0 NRESET NWRAP NOBRX DUPLEX TRFRAM TXPACE Table A–8. Network Command Register Bits Name Function NRESET...

  • Page 137: Network Serial I/O Register-Netsio @ 0X00 (Dio)

    Adapter Internal Registers Table A–8. Network Command Register Bits (Continued) Name Function TXPACE Transmit pacing (CSMA/CD): This bit allows pacing of transmitted CSMA/CD frames to improve network utilization of network file servers. When this bit is set, the pacing algo- rithm is enabled.

  • Page 138: Network Status Register-Netsts @ 0X00 (Dio)

    Adapter Internal Registers Table A–9. Network Serial I/O Register Bits (Continued) Name Function EDATA EEPROM SIO data: This bit is used to read or write the state of the EDIO pin. When ETXEN is set to 1, EDIO is driven with the value in this bit. When ETXEN is set to 0, this bit is loaded with the value on the EDIO pin.

  • Page 139: Network Status Mask Register-Netmask @ 0X00 (Dio)

    Adapter Internal Registers Table A–10. Network Status Register Bits (Continued) Name Function RXSTOP Receiver stopped: This bit indicates the completion of a receive STOP command. This bit is cleared by writing a 1 to its bit position. Writing a 0 has no effect. 19 –...

  • Page 140: Network Configuration Register-Netconfig @ 0X04 (Dio)

    Adapter Internal Registers A.3.5 Network Configuration Register–NetConfig @ 0x04 (DIO) This 16-bit register is used for ThunderLAN’s controller configuration. This register is only writable while the ThunderLAN controller is in reset. (NRESET = 0). All bits in this register are set to 0 on an Ad_Rst or when PRST# is as- serted.
  • Page 141 MTEST Manufacturing test: When this bit is set to 1, the adapter is placed into manufacturing test mode. Manufacturing test mode is reserved for Texas Instruments manufacturing test. Operation of the adapter with this bit set is undefined. PHY_En On-chip PHY enable: This bit is used to enable/disable the adapter’s on-chip 10Base-T...

  • Page 142: Manufacturing Test Register-Mantest @ 0X04 (Dio)

    This 16-bit register is used for manufacturing test. The options controlled by this register only take effect while the MTEST bit in the NetConfig register is set. The functions controlled by this register are for Texas Instruments manufacturing test only.

  • Page 143: General Address Registers-Areg_0-3 @ 0X10-0X24 (Dio)

    Adapter Internal Registers A.3.8 General Address Registers–Areg_0-3 @ 0x10–0x24 (DIO) The four general-purpose address registers, Areg_0 through Areg_3, are used to hold the adapter’s specific and group addresses. Each of the four reg- isters can be used to hold any 48-bit IEEE 802 address (specific or group, local or universal).

  • Page 144: Hash Address Registers-Hash1/Hash2 @ 0X28-0X2C (Dio)

    Adapter Internal Registers mode, functional addressing is supported through the general address regis- ters. If any address register contains a functional address (group/specific = 1; local/universal = 1; group/functional = 0), that register’s two MSbytes are compared normally, but its 31 LSBs are compared on a functional bit-match basis.

  • Page 145: Network Statistics Registers-@ 0X30-0X40 (Dio)

    Adapter Internal Registers A.3.10 Network Statistics Registers–@ 0x30–0x40 (DIO) The network statistics registers gather frame error information. Registers vary in size, depending on the frequency with which they increment, and may be 8, 16, or 24 bits wide. Reading a statistics register clears its contents after the read.

  • Page 146: Ethernet Error Counters

    Adapter Internal Registers Table A–14. Ethernet Error Counters Counter Definition Good Tx frames are without errors. This is a 24-bit counter. Good frames are transmitted more frequently than errored frames. Tx frames are aborted during transmission, due to frame data not being available (due to host bus latencies).

  • Page 147: Adapter Commit Register-Acommit @ 0X40 (Dio) (Byte 3)

    Adapter Internal Registers Figure A–7. Demand Priority Error Counters DIO Address Byte 3 Byte 2 Byte 1 Byte 0 0x30 Rx overrun Good Rx frames 0x34 Tx underrun Good Tx frames 0x38 Code error CRC error Deferred Tx frames frames frames 0x3C 0x40...

  • Page 148: Led Register-Ledreg @ 0X44 (Dio) (Byte 0)

    Adapter Internal Registers Table A–16. Adapter Commit Register Bits Name Function 31 – 28 Tx commit Transmit commit level: This nibble code indicates the commit size in use by the adapter level transmitter. The code indicates the number of bytes that must be in a channel’s FIFO before network transmission is started.

  • Page 149: Burst Size Register-Bsizereg @ 0X44 (Dio) (Byte 1)

    Adapter Internal Registers A.3.13 Burst Size Register–BSIZEreg @ 0x44 (DIO) (Byte 1) This register is used to set the receive and transmit burst sizes to be used by the adapter. This register is only writable while the ThunderLAN controller is in reset.

  • Page 150: Maximum Rx Frame Size Register-Maxrx @ 0X44 (Dio) (Bytes 2+3)

    Adapter Internal Registers A.3.14 Maximum Rx Frame Size Register–MaxRx @ 0x44 (DIO) (Bytes 2+3) Byte 3 Byte 2 Maximum Rx frame size (in units of 8 bits) This register is used to set the maximum size of received network frames. Frames larger than this size are not copied and are counted as Rx-overrun er- ror frames.

  • Page 151: Interrupt Disable Register - Intdis @ 0X48 (Dio) (Byte 0

    Adapter Internal Registers A.3.15 Interrupt Disable Register - INTDIS @ 0x48 (DIO) (BYTE 0) This register is used to disable RX EOC, RX EOF and TX EOC interrupts. TX EOF can be disabled by setting to Tx interrupt threshold value to a zero. This register is only written to while the ThunderLAN Controller is reset.

  • Page 152: A.4 10Base-T Phy Registers

    10Base-T PHY Registers A.4 10Base-T PHY Registers The 10Base-T PHY registers are indirectly accessible through the MII. This is a low-speed serial interface which is supported on ThunderLAN through the NetSio register in adapter DIO space. A host software program uses the MCLK, MTXEN, and MDATA bits in this register to implement the MII serial pro- tocol for the management interface.

  • Page 153: A.4.1 Phy Generic Control Register – Gen_Ctl @ 0X0

    10Base-T PHY Registers A.4.1 PHY Generic Control Register–GEN_ctl @ 0x0 Byte 1 Byte 0 AUTO AUTO RESET LOOPBK PDOWN ISOLATE DUPLEX Reserved RSRT TEST Table A–19. PHY Generic Control Register Bits Name Function RESET PHY reset: Writing a 1 to this bit causes the PHY to be reset. This bit is self-clearing. The bit returns a value of 1 when read until the internal reset is complete.

  • Page 154: 10Base-T Phy Registers

    10Base-T PHY Registers Table A–19. PHY Generic Control Register Bits (Continued) Name Function ISOLATE Isolate: When this bit is set (default), the PHY electrically isolates its data paths from the MII. In this state, it does not respond to the MTXD0–3, MTXEN, and MTXER pin inputs, and presents a high impedance on its MTCLK, MRCLK, MRXDV, MRXER, MRXD0–3, and MCOL pin outputs.

  • Page 155: Phy Generic Status Register-Gen_Sts @ 0X1

    10Base-T PHY Registers A.4.2 PHY Generic Status Register–GEN_sts @ 0x1 Byte 1 Byte 0 Reserved AUTOCOMPLT RFLT LINK JABBER Table A–20. PHY Generic Status Register Bits Name Function 100Base-T4 capable: Not supported 100Base-Tx full-duplex capable: Not supported 100Base-Tx half-duplex capable: Not supported 10Base-T full-duplex capable: This bit is hardwired to 1 to indicate that 10Base-T full duplex is supported.
  • Page 156 10Base-T PHY Registers Table A–20. PHY Generic Status Register Bits (Continued) Name Function JABBER Jabber detect: When read as 1 this bit indicates a 10Base-T jabber condition has been detected. A jabber condition is latched (held) until the register is read. This bit has no meaning if the AUI interface is selected.

  • Page 157: Phy Generic Identifier-Gen_Id_Hi/Gen_Id_Lo @ 0X2/0X3

    10Base-T PHY Registers A.4.3 PHY Generic Identifier–GEN_id_hi/GEN_id_lo @ 0x2/0x3 Byte 1 Byte 0 Organizationally unique identifier (OUI) OUI cont. Manufacturer’s model number Revision number These two hardwired 16-bit registers contain an identifier code for the TLAN 10Base-T PHY. GEN_id_hi contains 0x4000, GEN_id_lo contains 0x50xx, where the xx denotes the revision.

  • Page 158: Autonegotiation Advertisement Register-An_Adv @ 0X4

    10Base-T PHY Registers A.4.4 Autonegotiation Advertisement Register–AN_adv @ 0x4 Byte 1 Byte 0 Reserved TLRFLT Technology ability field Selector field Table A–21. Autonegotiation Advertisement Register Bits Name Function Autonegotiation next page: Reception / transmission of autonegotiation next pages is optional and not supported by this PHY. Reserved For internal use of the autonegotiation process.

  • Page 159: Autonegotiation Link Partner Ability Register-An_Lpa @ 0X5

    10Base-T PHY Registers A.4.5 Autonegotiation Link Partner Ability Register–AN_lpa @ 0x5 Byte 1 Byte 0 Link partner Link partner LPNXTPAGE Reserved LPRFLT technology ability field selector field Table A–22. Autonegotiation Link Partner Ability Register Bits Name Function LPNXTPAGE Link partner next page: When this bit, is set, the link partner indicates that it has another page to send.

  • Page 160: Autonegotiation Expansion Register-An_Exp @ 0X6

    10Base-T PHY Registers A.4.6 Autonegotiation Expansion Register–AN_exp @ 0x6 Byte 1 Byte 0 Reserved PARDETFLT LPNPABLE PAGERX LPANABLE Table A–23. Autonegotiation Expansion Register Bits Name Function 15 – 5 Reserved Read as 0 PARDETFLT Parallel detection fault: For multi-technology PHYs, this bit indicates multiple valid links. This PHY only supports a single technology (10Base-T) and so this bit should be ignored.

  • Page 161: Thunderlan Phy Identifier High/Low-Tlphy_Id @ 0X10

    10Base-T PHY Registers A.4.7 ThunderLAN PHY Identifier High/Low–TLPHY_id @ 0x10 This hardwired 16-bit register contains a TI assigned identifier code for the ThunderLAN PHY/PMIs. An additional identifier is required to identify non-802.3 PHY/PMIs, which are not otherwise supported by the 802.3u MII specification.

  • Page 162: Thunderlan Phy Control Register-Tlphy_Ctl @ 0X11

    Manufacturing test: When this bit is set to a 1, the PHY is placed into manufacturing test mode. Manufacturing test mode is reserved for Texas Instruments manufacturing test only. Operation of the PHY and this register is undefined when this bit is set.

  • Page 163: A.4.9 Thunderlan Phy Status Register – Tlphy_Sts @ 0X12

    10Base-T PHY Registers Table A–24. ThunderLAN PHY Control Register Bits (Continued) Name Function INTEN Interrupt enable: Writing a 1 to this bit allows the PHY to generate interrupts on the MII if the MINT bit is set. Writing a 0 to this bit prevents the PHY from generating any MII interrupts.

  • Page 164: Thunderlan Phy Status Register Bits

    10Base-T PHY Registers Table A–25. ThunderLAN PHY Status Register Bits (Continued) Name Function † POLOK Polarity OK: When this bit is high (default), the 10Base-T PHY receives valid (nonin- verted) link pulses. If this bit goes low, it indicates that a sequence of seven consecutive inverted link pulses has been detected.
  • Page 165 A-52...
  • Page 166 Appendix B Appendix A TNETE211 100VG-AnyLAN Demand Priority Physical Media Independent (PMI) Interface This appendix contains register definitions for the TNETE211 100VG-AnyLAN PMI interface. ThunderLAN uses these registers to store information on its in- ternal status and its communication with the host. This appendix describes the purpose and function of each register and provides many bitmaps and descrip- tions of individual bits.

  • Page 167: B.1 100Vg-Anylan Training

    100VG-AnyLAN Training B.1 100VG-AnyLAN Training The algorithm used to open ThunderLAN to the network depends on the net- work protocol in use. The demand priority protocol specified in IEEE 802.12 goes through a training process to open onto the wire. To open the controller the driver must: Enter VG training;...
  • Page 168 100VG-AnyLAN Training The following describes what the driver must do to successfully train: 1) Assert the INTEN bit in the TLPHY_ctl register to enable MII interrupts to ThunderLAN from the voice grade (VG) PHY 2) Ensure that ThunderLAN is not in copy all frames mode, copy short frames mode, or broadcast mode (CAF, CSF, and NOBRX bits in the NetCmd reg- ister) 3) Disable the multicast addresses contained in the HASH registers...

  • Page 169: Training Flowchart

    100VG-AnyLAN Training 8) The driver now waits for a status interrupt. The MASK7 bit in the NetMask register must be set for the status interrupt to reach ThunderLAN. 9) When this interrupt arrives, perform frame exchange Training involves the exchange of 24 consecutive training frames between the client and the hub.
  • Page 170 100VG-AnyLAN Training If the training frame passes these criteria, it is valid. The driver updates a counter showing the number of consecutive valid training frames passed. The driver also keeps a separate counter showing how many frames are left in the training window.

  • Page 171: B.2 Tnete211 Register Descriptions

    PHY implements seven internal registers, three of which are hard- wired. The diagram below shows the devices’ register map. The registers shown in gray are the generic registers as mandated by 802.3u. The registers shown in white are Texas Instruments specific registers. All other registers are read as 0s.

  • Page 172: Tnete211 Registers

    TNETE211 Register Descriptions Figure B–3. TNETE211 Registers Register Description PHY generic control register GEN_ctl 0x00 PHY generic status register GEN_sts 0x01 GEN_id_hi PHY generic identifier (high) 0x02 GEN_id_lo PHY generic identifier (low) 0x03 AN advertisement Not implemented 0x04 AN far end ability Not implemented 0x05 AN reserved...

  • Page 173: B.2.2 Phy Generic Status Register – Gen_Sts @ 0X1

    TNETE211 Register Descriptions Table B–1. PHY Generic Control Register Bits (Continued) Name Function PDOWN Power down: When this bit is set (default), the PHY is placed in a low-power consump- tion state. This bit resets the 802.12 MAC state machine to MAC0. It stops the Tx and †...

  • Page 174: B.2.3 Phy Generic Identifier – Gen_Id_Hi/Gen_Id_Lo @ 0X2/0X3

    0x4000/ 0x502x for this PMI device, where x denotes the PHY revision. B.2.4 ThunderLAN PHY Identifier High/Low–TLPHY_id @ 0x10 This hardwired 16-bit register contains a Texas Instruments-assigned identifi- er code for the ThunderLAN PHY/PMIs. An additional identifier is required to identify non-802.3 PHY/PMIs, which are not otherwise supported by the...

  • Page 175: Thunderlan Phy Control Register Bits

    TNETE211 Register Descriptions Table B–3. ThunderLAN PHY Control Register Bits Name Function IGLINK Ignore link: When this bit is set to 0, the 100VG-AnyLAN Demand Priority PHY expects to receive link pulses from the hub, and sets the LINK bit in the GEN_sts register to 0 if they are not present.

  • Page 176: Thunderlan Phy Status Register-Tlphy_Sts @ 0X12

    TNETE211 Register Descriptions B.2.6 ThunderLAN PHY Status Register–TLPHY_sts @ 0x12 Byte 1 Byte 0 MINT PHOK CONFIG RETRAIN LSTATE TRFRTO RTRIDL LRCV LSIL Table B–4. ThunderLAN PHY Status Register Bits Name Function MINT MII interrupt: This bit indicates an MII interrupt condition. The MII interrupt request is activated whenever this bit is set to 1.
  • Page 177 TNETE211 Register Descriptions Table B–4. ThunderLAN PHY Status Register Bits (Continued) Name Function TRFRTO Training frame time out: This bit indicates that the PMI is in training, the training frame has not been received in 273 s, and that another training frame should be sent. If the INTEN bit is also set, this causes an MII interrupt.
  • Page 178 Appendix C Appendix A TNETE100PM/TNETE110PM For information on the TNETE100PM and TNETE110PM implementations of ThunderLAN, please contact TLANHOT@micro.ti.com, which is listed on page v of this document.

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