Fixed-Cycle Timer Interrupt Function - Epson RX8130 CE Applications Manual

RX8130CE

14.2. Fixed-cycle Timer Interrupt Function

The fixed-cycle timer interrupt function generates an interrupt event periodically at any fixed cycle set between
244.14s and 65535 hours. This function can stop at one time and is available as a accumulative timer.
After the interrupt occurs, the /IRQ status is automatically cleared .
14.2.2. Related registers for function of fixed-cycle timer interrupt function
Address[h]
1A
1B
1C Extension Register
1D
1E Control Register0
Before entering operation settings, we recommend first clearing the TE bit to "0".
 When the fixed-cycle timer function is not being used, the fixed-cycle Timer Counter0,1 register can be used as a
RAM register. In such cases, stop the fixed-cycle timer function by writing "0" to the TE and TIE bits.
1) Down counter for fixed-cycle timer (Timer Counter 1, 0)
This register is used to set the default (preset) value for the counter. Any count value from 1(0001h)to
65535(FFFFh)can be set.
Be sure to write "0" to the TE bit before writing the preset value.
 When TE=0, read out data of timer counter is default (Preset) value.And when TE=1, read out data of
timer counter is just counting value.But, when access to timer counter data, counting value is not held.
Therefore, for example, perform twice read access to obtain right data, and a way to adopt the case that two
data accorded is necessary.
2) TSEL2, TSEL1, TESL0 bit
The combination of these three bits is used to set the countdown period (source clock) for this function.
TSEL2 TSEL1
( bit 2 ) ( bit 1 )
0 0
0 0
0 1
0 1
1 0
1) The /IRQ pin's auto reset time (tRTN) varies as shown above according to the source clock setting.
2) The first countdown shortens than a source clock.
When selected 4,096Hz / 64HZ / 1Hz as a source clock, one period of error occurs at the maximum.
When selected1/60Hz / 1/3600Hz as a source clock, 1Hz of error occurs at the maximum.
The example of the error of the first countdown: A value to preset is 0004h
TE
Internal source clock
Down counter
TF
Function bit 7
Timer Counter 0 128
Timer Counter 1 32768
FSEL1 FSEL0
Flag Register VBLF
TEST
TSEL0
Source clock
( bit 0 )
4096Hz /Once per 244.14 s
0
1 64Hz /Once per 15.625 ms
0 1Hz /Once per second
1 1/60Hz /Once per minute
0 1/3600 Hz
Designated cycle
Cycle error
初回周期誤差
4 3
bit 6 bit 5 bit 4
64 32 16
16384 8192 4096
USEL TE
 UF
TF
STOP UIE TIE
/Once per hour
2
Page18
bit 3 bit 2 bit 1
8 4 2
2048 1024 512
WADA TSEL2 TSEL1 TSEL0
AF RSF VLF
AIE TSTP TBKON TBKE
Auto reset time
tRTN (min)
122 s
7.57ms
7.57ms
7.57ms
7.57ms
1 4
TF Flag "0" ⇒ "1"
ETM50E-05

bit 0
1
256
VBFF