Using The Parallel Connector - Linear Technology DC1485A Demo Manual

USING THE PARALLEL CONNECTOR

Protocol
The DC1485A can be used without the DC590 system. If
a DC590 demo board is not connected the shift registers
on the DC1485A are disabled, allowing the user to clock
in data through the parallel connector (P1).
The data input register is loaded directly from the 18-bit
microprocessor bus (D0-D17 on the parallel connector)
by holding the _D/S pin low and then pulsing the _WR
pin low. The second register (DAC register) is loaded by
pulsing the UPD pin high, which copies the data held in
the input register into the DAC register. Note that updates
always include both data and span; but the DAC register
values will not change unless the input register values
have been changed by writing.
Loading the span input register is accomplished in a similar
manner, by holding the _D/S pin high and then bringing
the _WR pin low. The span and data register structures
are the same except for the number of parallel bits. The
span registers have three bits, while the data registers
have 18 bits.
Please see the LTC2757 data sheet for in depth timing
diagrams and more information about the communica-
tion protocol.
Parallel Pin Descriptions
D0-D17: DAC Input/Output Data Bits. These I/O pins set
and read back the DAC code. D17 is the MSB. D0 is the
LSB.
S0-S2: Span Input/Output. Pins S0, S1 and S2 are used to
program and to read back the output range of the DAC.
DEMO MANUAL DC1485A
_D/S: Data/Span Select: This pin is used to select acti-
vation of the data or span I/O pins (D0 to D17 or S0 to
S2, respectively), along with their respective dedicated
registers, for write or read operations. Update operations
ignore _D/S, since all updates affect both data and span
registers. For single-span operation, tie _D/S to GND.
READ: Read Pin. When READ is asserted high, the data
I/O pins (D0-D17) or span I/O pins (S0-S2) output the
contents of the selected register. For single-span operation,
readback of the span I/O pins is disabled.
UPD: Update and Buffer Select Pin. When READ is held low
and UPD is asserted high, the contents of the input registers
(both data and span) are copied into their respective DAC
registers. The output of the DAC is updated, refl ecting the
new DAC register values. When READ is held high, the
update function is disabled and the UPD pin functions as
a buffer selector—logic low to select the input register,
high for the DAC register.
_WR: Active Low Write Pin. A Write operation copies
the data present on the data or span I/O pins (D0-D17 or
S0-S2, respectively) into the input register. When READ
is high, the Write function is disabled.
MSPAN: Manual Span Control Pin. MSPAN is used to
confi gure the LTC2757 for operation in a single, fi xed
output range.
G: Ground Pin. (Note, if an IDE cable is used, Pin 21 is
often keyed on the connector and may be trimmed.)
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