Colorful BATTLE-AX Z490M-PLUS V20 Manual page 60

BATTLE-AX Z490M-PLUS V20
CAS Latency Time (tCL)
This controls the latency of the C A S, which determines the delay time (in
the time cycle) when the SDRAM starts reading after the receive
command.
RAS/ CAS Delay (tRCD)
This project is used to select the time lag between RAS (Row Address
Strobe) and CAS (Column Address Strobe) when reading and writing data
at the same bank. The shorter the set period, the faster the DRAM will
run.
ROW Precharge Time (tRP)
This project is used to control how long after the Precharge command is
sent out by SDRAM, the command must not be sent out again. It is
recommended that you use default values to keep the system stable.
Options: [2Clocks] [3Clocks] [4 Clocks] [5 Clocks] [6 Clocks].
Min Active RAS (tRAS) (SDRAM memory precharge delay)
This minimum value of R A S that controls the number of memory cycles
in S D R A M.
Read to Precharge (tRTP)
Select precharge time.
Row Cycle (tRC)
TRC stands for "SDRAM row cycle time," which is the minimum number of
clock cycles required for the entire process from precharge to activation of
the row unit.
Write Recover Time (TWR)
Select the write reply time after DRAM logs in to the last write, that is, the
pre-charge time after the last write.
RAS/RAS Delay (TRRD)
TRRD represents the "delay of row element to row element". This value
also indicates the time interval between sending activation instructions
(i.e. REF instructions) twice to the same row unit in the same bank. The
smaller the tRRD, the better. The lower latency means that the next bank
can be activated faster and read and write. However, due to the need for a
certain amount of data, too short delay will cause continuous data
expansion. For desktop computers, it is recommended that the TRRD value
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