Audio Interface Signals; Lvds And Edp Flat Panel Signals - Seco Qseven mQ7-C72 User Manual

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SDIO_CLK: Clock Line (output), 50MHz maximum frequency for High Speed Mode.

SDIO_CMD: Command/Response line. Bidirectional signal, electrical level +3.3V_RUN, used to send command from the Host to the connected card, and to send

the response from the card to the Host.

SDIO_WP: Write Protect input, electrical level +3.3V_RUN with 100k pull-down resistor. It is used to communicate the status of Write Protect switch of the external

SD card. Since microSD cards don't manage this signal, it is important that, when designing carrier boards with microSD slots, this signal must be tied to GND,

otherwise the OS will always consider the card as protected from writing.

SDIO_DAT[0÷3]: SD Card data bus. SDIO_DAT0 signal is used for all communication modes. SDIO_DAT[1÷3] signals are required for 4-bit communication mode.

3.2.8

Audio interface signals

µQ7-C72 module supports I2S audio format, thanks to native support offered by the processor to this audio codec standard.

Here following the signals related to AC'97/I2S Audio interface:

I2S_WS: I2S Word Select Signal. Output from the module to the Carrier board, electrical level +3.3V_RUN.

I2S_RST#: I2S Codec Reset. Active Low signal Output from the module to the Carrier board, electrical level +3.3V_RUN.

I2S_CLK: I2S Serial Data Clock signal. Output from the module to the Carrier board, electrical level +3.3V_RUN.

I2S_SDO: I2S Serial Data Out signal. Output from the module to the Carrier board, electrical level +3.3V_RUN.

I2S_SDI: I2S Serial Data In signal. Input to the module from the Carrier board, electrical level +3.3V_RUN.

All these signals have to be connected, on the Carrier Board, to an I2S Audio Codec. Please refer to the chosen Codec s Reference Design Guide for correct

implementation of audio section on the carrier board.

3.2.9

LVDS and eDP Flat Panel signals

All processors included in i.MX 8M Mini and Nano family provide a four-lane MIPI display serial interface operating up to a maximum bit rate of 1.5 Gbps. The MIPI-

DSI is used to implement a 18/24 bit Single/Dual Channel LVDS or, as a factory alternative, an eDP interface

ONLY ONE set of signals from the following two sets are present, dependent on the factory board configuration.

EITHER the signals for primary channel are LVDS:

LVDS_A0+ / LVDS_A0- : LVDS Channel #A differential data pair #0

LVDS_A1+/ LVDS_A1-: LVDS Channel #A differential data pair #1

LVDS_A2+/LVDS_A2-: LVDS Channel #A differential data pair #2

LVDS_A3+/ LVDS_A3-: LVDS Channel #A differential data pair #3

LVDS_A_CLK+ / LVDS_A_CLK-: LVDS Channel #A differential Clock

Q7-C72

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