Table 4-8, Questionable Condition Register Bit Assignment - Racal Instruments 1261B User Manual

High power intelligent mainframe vxi chassis
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1261B User Manual

Table 4-8, Questionable Condition Register Bit Assignment

Racal Instruments Ó 1995
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The Enable Registers for each attribute may be set with the
following commands (arbitrary register values are shown)
STAT:QUES:VOLT:ENAB
STAT:QUES:CURR:ENAB
STAT:QUES:TEMP:ENAB
STAT:QUES:TIME:ENAB
STAT:QUES:FREQ:ENAB
STAT:QUES:VXI:ENAB
Each of the monitored attributes have an Event Register and an
Enable Register.
ANDed together, and the result is Ored to form a status
summary bit. Each attribute is represented in the "Questionable
Condition" register by a single summary bit. The bit assignments
for the "Questionable Condition" register is shown in Table 4-8.
Bit
0
Voltage Event AND Enable bit or bits set
1
Current Event AND Enable bit or bits set
2
Time Event AND Enable bit or bits set
3
Not Assigned/always 0
4
Temperature Event AND Enable bit or bits set
5
Fan Speed Event AND Enable bit or bits set
6
Not Assigned/always 0
7
Not Assigned, always 0
8
Not Assigned, always 0
9
VXI Event AND Enable bit or bits set
10
Not Assigned, always 0
11
Not Assigned, always 0
12
Not Assigned, always 0
13
Not Assigned, always 0
14
Not Assigned, always 0
15
Not Assigned, always 0
-- Voltage Enable
127
-- Current Enable
31
-- Temperature Enable
7
-- Elapsed Time Enable
15
-- Fan Speed Enable
15
-- VXI Enable
255
For each attribute, the registers are logically
Set When
Using The Enhanced Monitoring System 4-19

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