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VersaLogic VL-486-4 Reference Manual

Industrial cpu card for the std 32 bus
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VL-486-4
Industrial CPU Card
for the STD 32 Bus

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Summary of Contents for VersaLogic VL-486-4

  • Page 1 Reference Reference Reference Reference Manual Manual Manual Manual VL-486-4 Industrial CPU Card for the STD 32 Bus...
  • Page 3 VL-486-4 Industrial CPU Card for the STD 32 Bus M486-4...
  • Page 5 All Rights Reserved Notice: Although every effort has been made to ensure this document is error-free, VersaLogic makes no representations or warranties with respect to this product and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose.

  • Page 7: Table Of Contents

    Table of Contents Other References ......................vii 1. Overview ........................... 1 Using This Manual ......................1 Introduction ........................1 PC/AT Compatibility..................... 1 STD BUS Compatibility..................1 On-Board Memory ....................2 Hard Disk and Floppy Disk Interface..............2 Digital I/O (Opto 22) Interface................2 COM Ports ......................
  • Page 8 Table of Contents RAM Configuration..................... 22 Compatible RAM Devices................... 22 CMOS RAM Configuration ................23 Memory Mapping ....................24 I/O Configuration ......................25 Using 8-Bit I/O Cards..................25 Using 10-Bit I/O Cards..................25 Using 16-Bit I/O Cards..................26 COM2 Configuration......................27 RS-232 Operation ....................
  • Page 9 J6 – DMA Control Signals Connector..............54 L1 – Speaker Connector ..................55 5. Register Descriptions......................57 Introduction ........................57 Register Summary ......................57 Direct Memory Access — Channel 1..............58 Direct Memory Access — Channel 2..............59 Direct Memory Access — Page Registers ............59 COM1 Serial Port ....................
  • Page 10 Table of Contents Special I/O Control Registers................82 Pattern Definition Registers ..................... 83 Pattern Polarity Register..................83 Pattern Transition Register .................. 83 Pattern Mask Register..................83 Port A and B Data Registers................84 Port C Data Register .................... 85 Counter/Timer Control Registers ................ 85 Counter/Timer Mode Specification Registers .............

  • Page 11: Other References

    Other References Chips and Technologies, Inc., (408)434-0600, 82C836 Chipset Data Book Chips and Technologies, Inc., (408)434-0600, 82C721 Universal Peripheral Controller II Data Book Zilog, Inc., (408)370-8000, Z8036 Z-CIO/Z8536 CIO Counter/Timer and Parallel I/O Unit Technical Manual STD Manufacturers Group, (408)723-5083, STD 32 Bus Specification and Designer’s Guide Texas Instruments (214)917-1264, TI486SXLC2 Data Book...

  • Page 13: Overview

    STD BUS C OMPATIBILITY The VL-486-4 CPU card complies with certain subsets of the STD 32 Bus specification that allow it to communicate with STD 80 compatible 8-bit and STD 32 compatible 16-bit I/O and memory cards. In addition, the card fully complies with the STD 80 Bus specification using a bus speed of 8.33 MHz.

  • Page 14: On-Board Memory

    LOPPY NTERFACE The VL-486-4 does not have hard disk or floppy disk interfaces. A Flash File System is included which allows the CPU to boot from Drive A. Software is pre-installed on the FFS to network the CPU with a desktop IBM PC using RS-232.

  • Page 15: Real Time Clock With Cmos Ram

    DMA C ONTROLLERS The VL-486-4 has two DMA controllers which provide a total of eight DMA channels (four 8-bit channels and four 16-bit channels.) One 8-bit or 16-bit channel (jumper selectable) is available for general purpose use through a front-plane DMA connector. The remaining channels are accessible only by software.

  • Page 16: Technical Specifications

    EPROM and Flash EEPROM: 200 ns or faster Bus Compatibility: STD 80: Full compliance, 8.33 MHz bus speed STD 32: Permanent Master; SA16, SA8-I, MB, MX STD 32: Temporary Master; SA16, SA8-I, MB, {MX} Specifications are subject to change without notice. 4 – Overview VL-486-4 Reference Manual...

  • Page 17: Technical Support

    Technical Support Technical Support If you have problems that this manual can’t help you solve, contact VersaLogic for technical support at 1-800-824-3163. You can also reach VersaLogic by e-mail at info@versalogic.com. VL-486-4 Reference Manual Overview – 5...

  • Page 19: Dos Based Quick Start

    A minimum DOS based run time system requires the CPU card, a BIOS, and a boot device (the flash file system is the only boot device available on the VL-486-4) containing an operating system and an application program. In many cases a video card, keyboard and monitor are added to this list, however, the VL-486-4 does not demand their presence in order to boot.

  • Page 20: Installation

    Installation Installation Before installing the VL-486-4 CPU card in a card cage, you must confirm that the on-card battery is activated. Caution Electrostatic discharge (ESD) can damage cards, disk drives, and other components. Do the installation procedures described in this chapter only at an ESD workstation.

  • Page 21: Jumper Locations

    Jumper Locations Jumper Locations Note Jumpers and resistor packs shown in as-shipped configuration. Figure 1. VL-486-4 CPU Card Layout VL-486-4 Reference Manual DOS Based Quick Start – 9...

  • Page 22: Card Installation

    Card Installation Card Installation A typical VersaLogic DOS based system consists of a six-slot V32-06T Card Cage, populated with: • VL-486-4 CPU Card • VL-SVGA-1 Card A VGA compatible monitor and a PC/AT compatible keyboard plug into the VL-SVGA-1 card.

  • Page 23: Monitor And Keyboard Installation

    Monitor and Keyboard Installation A VGA monitor and IBM-AT compatible keyboard should be connected to the VL-SVGA-1 card as shown . Figure 2. Jumpers/Connections for a VL-SVGA-1 Using a VGA Monitor VL-486-4 Reference Manual DOS Based Quick Start – 11...

  • Page 24: Cable Installation

    Cable Installation Cable Installation To bring the header connectors on the VL-486-4 CPU card out to PC/AT and industry standard pinouts, the VersaLogic cable assemblies listed below are required. Table 2: Cable Assemblies. Connector Part # Description Connects to: J1 COM1 9575 1 ft.

  • Page 25: Cmos Setup Options

    ONFIGURATION This option goes to another menu which allows you to change the following: • Date, Time • Floppy Drive and Hard Drive types (not applicable on the VL-486-4) • Console (VGA Card or Serial Port) CMOS C DVANCED ONFIGURATION This option goes to another menu which allows you to change the following: •...

  • Page 26: Reset Cmos To Factory Defaults

    CMOS checksum is updated and the CPU card is rebooted. CMOS ITHOUT HANGING This option acts like a cancel function. Use it to exit Setup without changing CMOS RAM. 14 – DOS Based Quick Start VL-486-4 Reference Manual...

  • Page 27: Clearing The Cmos Ram

    Do not apply power to the CPU card with jumper V5[1-2] installed, doing so may damage the chipset and void the warranty. Jumper V5[1-2] is only briefly used to clear the CMOS RAM. Figure 3. CMOS RAM Jumper VL-486-4 Reference Manual DOS Based Quick Start – 15...

  • Page 29: Configuration

    Configuration This chapter describes how to configure the on-board options for the VL-486-4 CPU card. Configuration involves both hardware (jumper) and software (chipset) configuration. The jumpers configure the circuitry on the card for various modes of operation. The software configuration completes the process by initializing the circuits within the chipset. This chapter does not describe how to initialize the standard DOS peripheral devices such as the serial ports and disk drive interfaces.

  • Page 30: Jumper Block Locations

    Hardware Jumper Summary UMPER LOCK OCATIONS Note Jumpers and resistor packs shown in as-shipped configuration. Figure 5. Jumper Block Locations 18 – Configuration VL-486-4 Reference Manual...
  • Page 31 — Connects IPC signal to STD Bus INTRQ* (P44) — Disconnects IPC from INTRQ* V7[2-3] IPC Configuration (IPC / INTRQ4* interconnect) — Connects IPC signal to STD Bus INTRQ4* (P05) — Disconnects IPC from INTRQ4* VL-486-4 Reference Manual Configuration – 19...
  • Page 32 — Connects Counter / Timer 2 to IRQ15 — Disconnects CTC2 from IRQ15 V13[2-3] Interrupt Configuration (IRQ15 / Digital I/O Interrupt interconnect) — Connects Digital I/O Interrupt to IRQ15 — Disconnects DIO Interrupt from IRQ15 20 – Configuration VL-486-4 Reference Manual...

  • Page 33: Memory Configuration

    The on-board ROM sockets (U10 and U11) accept one or two 128Kx8, 256Kx8, or 512Kx8, 32 pin plastic or 32 pin J-lead ceramic part(s). An extractor tool (such as VersaLogic part PLCC number 9685) is required to remove the rectangular...

  • Page 34: Ram Configuration

    The following (non exhaustive) list of memory devices can be used. All parts must be 70 ns or faster, and must use 1024 refresh cycles. Note The 1M x 16 RAM is available from VersaLogic as part number 9650. Caution VersaLogic makes no representation of the suitability, reliability, or availability of any of the following memory devices.

  • Page 35: Cmos Ram Configuration

    CMOS RAM C ONFIGURATION The VL-486-4 CPU card is shipped with the battery disconnected. Since the battery provides backup power to the CMOS RAM and the real time clock circuits when the card is powered down, the battery must be activated before putting the card in service.

  • Page 36: Memory Mapping

    EMORY APPING The memory map of the VL-486-4 is arranged as follows. Page 7 of Flash 0 is the system BIOS, and always appears from 0F0000h to 0FFFFFh. Bits D3–D0 in the MPCR register select which Flash ROM page is mapped into the Flash Frame (0E0000h to 0EFFFFh). See MPCR register description on page 72 for further information.

  • Page 37: I/O Configuration

    SING ARDS I/O cards which only decode 8 address bits (A0 - A7) will work properly with the VL-486-4 provided the STD Bus signal IOEXP is decoded low on the I/O card. IOEXP will be driven low in the I/O address range FC00h to FFFFh. The I/O card can be configured to use any 8-bit address in the range 00h to FFh.

  • Page 38: Using 16-Bit I/O Cards

    I/O Configuration 16-B I/O C SING ARDS I/O cards which decode all 16 address bits (A0 - A15) will work properly with the VL-486-4 when addressed in the following I/O ranges: • − 01EFh 0100h • − 027Fh 0200h •...

  • Page 39: Com2 Configuration

    Removing V4[9-10] leaves the data circuit unterminated so that COM2 can be used as an intermediate station in an RS-485 multidrop system. When COM2 is used in multidrop operations, remove jumper V4[9-10] from all stations except both ends of the line. VL-486-4 Reference Manual Configuration – 27...
  • Page 40 — RS-422 mode. Permanently enables the differential line driver. V4[9-10] RS-422/485 Transmission Line Termination — Terminates data circuit with 100 Ω resistor (RS-422, or RS-485 endpoint stations only) — Leaves data circuit unterminated (RS-485 intermediate multidrop stations only) 28 – Configuration VL-486-4 Reference Manual...

  • Page 41: Opto 22 Rack Configuration

    Opto 22 Rack Configuration Opto 22 Rack Configuration The VL-486-4 card has 16 digital I/O lines that can be independently programmed as inputs or outputs. The I/O connector is compatible with 8 and 16 position modular I/O racks. OWER ONTROL The VL-486-4 board includes provisions for powering the external I/O rack assembly with +5 volts at 500 ma.

  • Page 42: Multiprocessor Configuration

    Multiprocessor Configuration Multiprocessor Configuration The VL-486-4 CPU card supports multiple master operation for systems requiring additional processing capability or for “smart I/O” operations. In a multiple master system, one CPU must be configured as a permanent master and other CPUs are configured as temporary masters. In this scheme, a bus arbiter plugged into Slot X is used to arbitrate access to the bus.

  • Page 43: Resistor Pack Configuration

    SYSRESET* arriving from the permanent master via the bus. A temporary master should never respond directly to PBRESET* nor drive SYSRESET*. Dual Master — Same as temporary master mode. VL-486-4 Reference Manual Configuration – 31...

  • Page 44: Interrupt Configuration

    Interrupt Configuration Interrupt Configuration Six three-position jumper blocks are used to configure the interrupt sources on the VL-486-4. Each jumper block is used to select one of two interrupt sources and route it to the interrupt controller. Wire wrap techniques can be used on V9 through V13 to route interrupt sources to the CPU’s IRQ inputs if the factory provided jumpers do not provide suitable connections.

  • Page 45: Interrupt Configuration Jumpers

    — Connects Counter / Timer 2 to IRQ15 — Disconnects CTC2 from IRQ15 V13[2-3] Interrupt Configuration (IRQ15 / Digital I/O Interrupt interconnect) — Connects Digital I/O Interrupt to IRQ15 — Disconnects DIO Interrupt from IRQ15 VL-486-4 Reference Manual Configuration – 33...

  • Page 46: Std Bus Interrupt Signals

    IRQ12 by inserting jumper V12[1-2]. INTRQ4* VBAT General purpose INTRQ4* can be jumpered to carry the Interprocessor Communications Interrupt (IPC) between multiple CPU’s by inserting jumper V7[2-3]. The IPC signal is hardwired to IRQ5. 34 – Configuration VL-486-4 Reference Manual...

  • Page 47: Cpu Interrupt Request Inputs

    LPT 2 Hardwired IPC Interrupts. IRQ6 Floppy Disk No Connection Internal signal, not available to the outside world. Non-DOS users should mask this interrupt. IRQ7 LPT1 Hardwired Internal signal, not available to the outside world. VL-486-4 Reference Manual Configuration – 35...
  • Page 48 IRQ14 Hard Disk No Connection Internal signal, not available to Drive the outside world. IRQ15 Unassigned CIO Chip IRQ15 can receive interrupts from the on-board Counter/Timer #2 or from the Digital I/O circuitry. 36 – Configuration VL-486-4 Reference Manual...

  • Page 49: Interprocessor Communications Interrupt Configuration

    Table 16: Non-Maskable Interrupt Jumper Jumper Description Block Shipped V8[5-6] Non-Maskable Interrupt / BUS Interconnect — Connects STD Bus NMIRQ (P46*) to CPU NMI input — CPU ignores activity on STD Bus NMIRQ (P46*) VL-486-4 Reference Manual Configuration – 37...

  • Page 50: Dma Configuration

    J6. Table 17: DMA Configuration Jumpers Jumper Block Description Shipped DMA Configuration — DMA from connector J6 serviced by DMA Channel 7 (16-Bit) — DMA from connector J6 serviced by DMA Channel 3 (8-Bit) 38 – Configuration VL-486-4 Reference Manual...

  • Page 51: Dma Channel Allocation

    DMA Channel Allocation DMA Channel Allocation The VL-486-4 has two DMA controllers which provide a total of eight DMA channels (four 8-bit channels and four 16-bit channels.) One 8-bit or 16-bit channel (jumper selectable) is available for general purpose use through a front-plane DMA connector (J6). The remaining channels are accessible only by software.

  • Page 52: Board Initialization

    Controller II data books listed in “Other References” on page v. The chips in the Chips & Technologies chipset, the 82C836 and the 82C721, have different methods of register access which are described in the following sections. 40 – Configuration VL-486-4 Reference Manual...

  • Page 53: 82C836 Initialization

    EMS Control Register Laptop Features Fast Video Control — — Fast Video RAM Enable — — High Performance Refresh CAS Timing for DMA/Master * When DRAM parity detection is enabled, this should be 41h. VL-486-4 Reference Manual Configuration – 41...

  • Page 54: 82C721 Initialization

    Texas Instruments 486SXLC Data Book listed in “Other References” on page v. To initialize the 486SXLC: 1. Output the index number to port 0022h. 2. Output the initialization data to port 0023h (see table). 3. Repeat steps 1 and 2 for all the registers. 42 – Configuration VL-486-4 Reference Manual...

  • Page 55: Ram Refresh Initialization

    The DRAM refresh must be initialized by sending the data listed in table below directly to the ports indicated. Table 22: Refresh Initialization Port Initialization Number Data Description Mask DRAM Parity Interrupt Refresh Timer Command Refresh Time Constant VL-486-4 Reference Manual Configuration – 43...

  • Page 57: Installation

    Dispose of used batteries promptly. Activating the Battery The VL-486-4 CPU card is shipped with the battery disconnected. Since the battery provides backup power to the CMOS RAM and the real time clock circuits when the card is powered down, the battery must be activated before putting the card in service.

  • Page 58: Card Installation

    Card Insertion and Extraction NSTALLATION The VL-486-4 card can be used alone, as a single board computer; as the only computer in a card cage with other I/O cards; or in conjunction with several other CPUs in a multiprocessing arrangement.

  • Page 59: External Connections

    External Connections External Connections This chapter describes the external interfaces available on the VL-486-4 CPU card. ONNECTOR UNCTIONS Table 23: Connector Functions Connector Function COM1 Serial Port Connector Digital I/O Connector LPT1 Parallel Port Connector COM2 Serial Port Connector Counter/Timer, Digital I/O and...

  • Page 60: Mating Connectors And Cable Assemblies

    SSEMBLIES Connections to the VL-486-4 can be made using flat ribbon cable and mass-terminated mating connectors. To bring the connectors on the VL-486-4 card out to standard PC/AT style pinouts, the VersaLogic cable assemblies listed below can be used. Schematic diagrams for the cable assemblies are shown on the following pages.

  • Page 61: Cable Assembly Diagrams

    External Connections ABLE SSEMBLY IAGRAMS The following diagrams show how to construct the cables which attach to the external connectors. Figure 9. Cable Assemblies VL-486-4 Reference Manual Installation – 49...

  • Page 62: J1, J4 - Serial Port Connectors

    — — — Ground Ground Ground Ground — RD2– Receive Data TD2/RD2– Transmit/Receive Out/In Negative Data Negative RD2+ Receive Data TD2/RD2+ Transmit/Receive Out/In Positive Data Positive — — — — — — — — 50 – Installation VL-486-4 Reference Manual...

  • Page 63: J2 - Digital I/O Connector

    +5V output to power the Opto 22 interface rack or other external equipment. If the I/O rack is powered by a separate external supply, the power jumper on the I/O rack or the V1 jumper must be removed. This output is fused with a resettable polyfuse rated at 1A. VL-486-4 Reference Manual Installation – 51...

  • Page 64: J3 - Lpt1 Parallel Port Connector

    Ground Ground — Data bit 5 In/Out Ground Ground — Data bit 6 In/Out Ground Ground — Data bit 7 In/Out PBSY Port busy Data bit 8 In/Out Paper end ACK* Acknowledge SLCT Select 52 – Installation VL-486-4 Reference Manual...

  • Page 65: J5 - Counter/Timer - Digital I/O - Interrupt Connector

    If jumper V12[2-3] is inserted, a low level (or high-to-low transition) applied to the FPI3* pin will request an interrupt via IRQ12. In DOS configuration this will cause an INT 74h resulting in a dispatch through the interrupt vector at 0000:01D0h. VL-486-4 Reference Manual Installation – 53...

  • Page 66: J6 - Dma Control Signals Connector

    STD Bus. The DMA controller receives the data and saves it in memory. TC* — Terminal Count. A low level on this TTL output signal indicates that the count register has decremented from 0000h to FFFFh, signaling completion of a block of DMA transfers. 54 – Installation VL-486-4 Reference Manual...

  • Page 67: L1 - Speaker Connector

    External Connections L1 – S PEAKER ONNECTOR Connector L1 is provided for connecting an 8Ω speaker to the card. Table 31: Speaker Connector Pinout. Signal Name Function Timer 2 Out Speaker drive Ground Ground VL-486-4 Reference Manual Installation – 55...

  • Page 69: Register Descriptions

    “Other References” on page v. Information on the registers internal to the CPU chip can be found in the TI486SXLC2 data book. Register Summary The tables in this section list all programmable registers on the VL-486-4 CPU card. They are organized in the following groups: Table 32: Programmable Registers...

  • Page 70: Direct Memory Access - Channel 1

    DMA Single Bit Mask Register DMAMODEA 000Bh DMA Mode Register DMACBPA 000Ch DMA Clear Byte Pointer DMAMCA 000Dh DMA Master Clear DMACMA 000Eh DMA Clear Mask Register DMAWAMA 000Fh DMA Write All Mask Register Bits 58 – Register Descriptions VL-486-4 Reference Manual...

  • Page 71: Direct Memory Access - Channel 2

    0087h DMA Channel 0 Page Register DMA6PG 0089h DMA Channel 6 Page Register DMA7PG 008Ah DMA Channel 7 Page Register DMA5PG 008Bh DMA Channel 5 Page Register RAPREG 008Fh Refresh Address Page Register VL-486-4 Reference Manual Register Descriptions – 59...

  • Page 72: Com1 Serial Port

    Interrupt Identification Register B LCRB 02FBh Line Control Register B MCRB 02FCh Modem Control Register B LSRB 02FDh Line Status Register B MSRB 02FEh Modem Status Register B SCRB 02FFh Scratchpad Register B 60 – Register Descriptions VL-486-4 Reference Manual...

  • Page 73: Lpt1 Parallel Port

    Configuration Register 0 03F1h Configuration Register 1 03F1h Configuration Register 2 03F1h Configuration Register 3 Table 40: 82C836 Configuration Registers Mnemonic Address Name ICRI 0022h Internal Register Index ICRD 0023h Internal Register Data VL-486-4 Reference Manual Register Descriptions – 61...

  • Page 74: Floppy Disk Drive Controller

    01F4h Cylinder Number Register Low IDECNH 01F5h Cylinder Number Register High IDEDH 01F6h Drive/Head Register IDEST 01F7h Status Register IDECMD 01F7h Command Register IDEDIR 03F7h Digital Input Register IDEFDR 03F6h Fixed Disk Register 62 – Register Descriptions VL-486-4 Reference Manual...

  • Page 75: Interrupt Controller - Master

    Operation Command Word 2 (Priority & Finish Control) OCW3B 00A0h Operation Command Word 3 (Mode Control) ISRB 00A0h In-Service Register IRRB 00A0h Interrupt Request Register IPWB 00A0h Interrupt Poll Word IMRB 00A1h Interrupt Mask Register VL-486-4 Reference Manual Register Descriptions – 63...

  • Page 76: Counter/Timers

    Real Time Clock Data Port CIO C Table 47: CIO Registers Mnemonic Address Name CIOCONTROL 00E4h Control Port CIOPORTA 00E5h Port A Data Port CIOPORTB 00E6h Port B Data Port CIOPORTC 00E7h Port C Data Port 64 – Register Descriptions VL-486-4 Reference Manual...

  • Page 77: Special Control Register

    Jumper in. PM* = 1 Jumper out. WDOGEN Watchdog Enable — Enables and disables the watchdog timer reset circuit. WDOGEN = 0 Disables the watchdog timer. WDOGEN = 1 Enables the watchdog timer. VL-486-4 Reference Manual Register Descriptions – 65...

  • Page 78: Watchdog Timer Hold-Off Register

    If the watchdog timer is enabled, software must periodically refresh the watchdog timer at a rate faster than the timer is set to expire (250 ms). Writing a 5Ah to WDHOLD resets the watchdog time-out period, preventing the CPU from being reset for the next 250 ms. 66 – Register Descriptions VL-486-4 Reference Manual...

  • Page 79: Map And Paging Control Register

    50000h to 5FFFFh 60000h to 6FFFFh 70000h to 7FFFFh 80000h to 8FFFFh 90000h to 9FFFFh A0000h to AFFFFh B0000h to BFFFFh C0000h to CFFFFh D0000h to DFFFFh E0000h to EFFFFh F0000h to FFFFFh VL-486-4 Reference Manual Register Descriptions – 67...

  • Page 81: Cio Chip

    The text in this section has been copied directly from the Zilog Technical Manual. Several functions on the CIO chip are not implemented at the hardware level on the VL-486-4 CPU card, and some functions are not supported by VersaLogic. The table below describes these exceptions:...

  • Page 82: Features

    Status register. After the port is configured, this is the only register that needs to be accessed frequently. To facilitate initialization, the port logic is designed so that registers associated with an unrequired capability are ignored and do not have to be programmed. 70 – CIO Chip VL-486-4 Reference Manual...

  • Page 83: Portc

    CIO. Each description includes the register address, the operation of the individual bits, and the state of the register after a reset (hardware or software). For simplicity, the descriptions assume that the data path polarity of each bit is programmed to be non-inverting. VL-486-4 Reference Manual CIO Chip – 71...

  • Page 84: Cio Registers

    Port B Handshake Specification CIOBDPP Port B Data Path Polarity CIOBDD Port B Data Direction CIOBSIC Port B Special I/O Control CIOBPP Port B Pattern Polarity CIOBPT Port B Pattern Transition CIOBPM Port B Pattern Mask 72 – CIO Chip VL-486-4 Reference Manual...

  • Page 85: Register Access

    I/O port addresses: Table 50: Port A/B/C Direct Access Addresses Register Address Port A Data Port 00E5h Port B Data Port 00E6h Port C Data Port 00E7h VL-486-4 Reference Manual CIO Chip – 73...

  • Page 86: Master Control Registers

    When the CIO chip is reset, all bits in all device registers are forced to 0 except RESET, which is set to 1. All bits in the Master Interrupt Control register are Read/Write. 74 – CIO Chip VL-486-4 Reference Manual...
  • Page 87 No Vector — Inhibits hardware vector generation during interrupt acknowledge cycle. Since CIO generated hardware interrupt vectors are not implemented on the VL-486-4, this bit should be set to 1 for normal operation. NV = 0 If NV is written with 0, the interrupt vector is output as usual.

  • Page 88: Master Configuration Control Register

    (however, if IP was already set, clearing CT1E does not clear IP), the Count In Progress (CIP) flag is cleared, Read Counter Control (RCC) is forced to 0, and all trigger inputs are ignored. CT2E = 1 Counter/timer 2 functions normally. 76 – CIO Chip VL-486-4 Reference Manual...
  • Page 89 Counter/Timers 1 and 2 are linked. The Counter/Timers must be linked before they are enabled. Mode Counter/Timers are independent Counter/Timer 1's output (inverted) gates Counter/Timer 2 Counter/Timer 1's output (inverted) triggers Counter/Timer 2 Counter/Timer 1's output (inverted) is Counter/Timer 2's count input VL-486-4 Reference Manual CIO Chip – 77...

  • Page 90: Port Mode Specification Register

    LPM = 1 Causes the port to latch the input data present at the port when a pattern match is detected. DTE = 0 Not supported. DTE = 1 Not supported. 78 – CIO Chip VL-486-4 Reference Manual...

  • Page 91: Port Handshake Specification Registers

    A reset forces ORE to 1 and all other bits to 0. All bits are readable and four are writable. VL-486-4 Reference Manual CIO Chip – 79...
  • Page 92 (a second match before a previous match is Write) acknowledged) are ignored. However, if IOE is 1, such errors will cause IP to be set and will halt normal operation of the port until the error condition is dealt with. 80 – CIO Chip VL-486-4 Reference Manual...

  • Page 93: Bit Path Definition Registers

    CIOADD (READ/WRITE) 23H CIOBDD (READ/WRITE) 2BH CIOCDD (READ/WRITE) 06H Each of the Data Direction registers define the direction of data flow for the individual bits of its port if configured as a bit port. VL-486-4 Reference Manual CIO Chip – 81...

  • Page 94: Special I/O Control Registers

    A 1 in this register defined the output as open-drain; no pull-up transistor is provided. The value programmed in this register applies to all output modes, independent of utilization. A reset forces all bits to 0. All bits are read/write. 82 – CIO Chip VL-486-4 Reference Manual...

  • Page 95: Pattern Definition Registers

    High level (VCC) on an input pin programmed as inverting matches a 0 specification. Similarly, an output written with a 1 matches a 1 specification even if it is programmed inverting and the output pin is at a low voltage level. VL-486-4 Reference Manual CIO Chip – 83...

  • Page 96: Port A And B Data Registers

    If so enabled, it is used by the bit port to latch data when a pattern match is detected. The individual bits of the port data registers map directly onto the port I/O pins (bit 0 of the Port A Data register corresponds to the PA0 pin, etc.). 84 – CIO Chip VL-486-4 Reference Manual...

  • Page 97: Portc Data Register

    Each Counter/Timer Mode Specification register contains the bits that define its counter/tier's mode of operation and specify the external control and status lines to provide for it. A reset forces all bits to 0. All bits are read/write. VL-486-4 Reference Manual CIO Chip – 85...
  • Page 98 D1-D0 DCS1-DCS0 Output Duty Cycle Selects — These two bits select the output duty cycle. DCS1 DCS0 Output Duty Cycle Pulse Output One-Shot Output Square-Wave Output DO NOT USE 86 – CIO Chip VL-486-4 Reference Manual...

  • Page 99: Counter/Timer Command Status Registers

    (in most cases) will be the register most often accessed. A reset forces all bits to 0. The detailed bit descriptions will discuss whether or not a bit can be read or written. VL-486-4 Reference Manual CIO Chip – 87...
  • Page 100 Counter/Timer is enabled in the Master Configuration Control register (CT1E, CT2E, or CT3E). RCC can be cleared automatically by reading the least- significant byte of the CRR or by disabling the counter/timer via the corresponding enable bit. 88 – CIO Chip VL-486-4 Reference Manual...

  • Page 101: Counter/Timer Time Constant Registers

    However, care must be taken when writing them so that a trigger does not occur while the time constant value is changing. A reset does not effect the Time Constant register. VL-486-4 Reference Manual CIO Chip – 89...

  • Page 102: Counter/Timer Current Count Registers

    Interrupt Vector register can be returned if the vector is programmed to include status. This does not affect the value written to the Interrupt Vector register. 90 – CIO Chip VL-486-4 Reference Manual...

  • Page 103: Current Vector Register

    1. If no enabled interrupts are pending, a pattern of all 1’s is output. This is useful in a polled environment or when CPU does not read vectors. This register is a read-only register. Since a reset disables all interrupts, reading the Current Vector register after a reset will return all 1s. VL-486-4 Reference Manual CIO Chip – 91...

  • Page 104: I/O Port Operation

    Reading the data register of the bit port returns the state of all bits, outputs as well as inputs. IMPLE PERATION The port’s Data Direction register specifies the direction of data flow for each bit of a bit port. A 1 specifies an input bit; a 0 specifies an output bit. 92 – CIO Chip VL-486-4 Reference Manual...

  • Page 105: Bit Port Pattern-Recognition Operation

    (LPM = 0) is supported when OR-PEV is specified. In all modes, the port’s IP bit is set and an interrupt generated (if enabled) when the pattern match is detected. The IP can only be cleared by a command to the Port Command and Status register. VL-486-4 Reference Manual CIO Chip – 93...

  • Page 106: Counter/Timer Operation

    Lines used for counter/timer I/O have the same characteristics as simple input lines. They can be specified as inverting or non-inverting, and can be read and used with the pattern-recognition logic. They can also include the 1’s catcher input. 94 – CIO Chip VL-486-4 Reference Manual...

  • Page 107: Counter/Timer Sequence Of Events

    Clearing an enable bit will not clear an existing IP that is set—it will only inhibit the IP from being set again. Clearing the enable bit will clear the Read Counter Control bit, causing the Current Count register to follow the down-counter. VL-486-4 Reference Manual CIO Chip – 95...

  • Page 108: Starting The Counter/Timer

    Control register. If any of the gate inputs go Low (0), the countdown halts. It resumes when all gate inputs are 1 again. The gate function does not affect the trigger function. The gate functions as the logical AND of all the potential gates. 96 – CIO Chip VL-486-4 Reference Manual...

  • Page 109: Ending Condition

    IP is already set, an internal error flag is set. As soon as IP is cleared, it is forced to a 1 along with the Interrupt Error (ERR) flag. Errors that occur after the internal flag is set are ignored. ERR is cleared to 0 when the corresponding IP is cleared. VL-486-4 Reference Manual CIO Chip – 97...

  • Page 110: Counter/Timer Output

    Counter/Timer 1 drives Counter/Timers 2’s count input, Counter/Timer 2 must be programmed with its external count input disabled (ECE = 0). The initialization procedure, then, is the same as for individual counter/timers, except that the linking bits need to be appropriately set. 98 – CIO Chip VL-486-4 Reference Manual...

  • Page 111: Interrupt Operation

    (highest to lowest): Counter/Timer 3, Port A, Counter/Timer 2, Port B, and Counter/Timer 1. Interrupts generated by the CIO are routed to the VL-486-4 interrupt controller on IRQ15 via jumper block V13[1-2].

  • Page 112: Identification Of The Highest-Priority Interrupt Request

    NTERRUPT EQUEST Since CIO hardware interrupt vectors are not supported on the VL-486-4, the Current Vector register facilitates the identification of the interrupting source. When read, the data returned is the same as the interrupt vector that would normally be provided during an Interrupt Acknowledge cycle based on the highest IP set.

  • Page 113: Interrupt Operation

    Even if the state of the CIO is not known, the following sequence will reset it. CIOCTL Insures state 0 or reset state CIOCTL,0 Write pointer or clear reset CIOCTL State 0 CIOCTL,0 Write pointer CIOCTL,1 Write reset CIOCTL,0 Clear reset VL-486-4 Reference Manual CIO Chip – 101...

  • Page 114: Enable Bits Operation

    IPs cannot be set, REQUEST and WAIT cannot be asserted, and all output remain high impedance; the handshake lines are ignored until Port C is enabled; and the counter/timers cannot be triggered until their enable bits are set. 102 – CIO Chip VL-486-4 Reference Manual...

  • Page 115: Interrupt Code Example

    (55h) is detected on Port B. It is assumed that a hardware loopback cable is installed causing values written to Port A to "come back in" on Port B. // ======================================================================= // VersaLogic Test Program for 486-4 I/O to the Z8536 Chip // ======================================================================= #include <dos.h>...
  • Page 116 ("Check value of 'Current Vector Register' before sending 55h\n"); outportb(0xE7, 0x1F); in_val1 = inportb(0xE7); printf ("Output E7, 1Fh; returned value = %x\n", in_val1); // Output value 55h from Port A to Port B, should cause an interrupt printf ("Ports A/B value=0x55\n"); 104 – CIO Chip VL-486-4 Reference Manual...
  • Page 117 Programming outportb(0xE6, 0x55); in_val1 = (0x00FF & inportb(0xE5)); printf ("Output E6, 55h; Read in from E5 = %x\n", in_val1); VL-486-4 Reference Manual CIO Chip – 105...
  • Page 118 ("Output E7, 1Fh; returned value = %x\n", in_val1); /* ---------- End of test ----------- */ in_val1 = inportb(0xE7); // put state machine into state 1 outportb(0xE7, 0x01); // Disable ports A,B, & C outportb(0xE7, 0x00); 106 – CIO Chip VL-486-4 Reference Manual...

  • Page 119: Appendix A - Schematic

    RP16B RP17F RP18G RP17E RP18E RP17D RP18D RP17C RP18C RP19F RP18B RP17B RP18A RP20G RP17A RP20F RP19D RP20E RP20D RP20C STD32P RP13E RP14C RP14A RP16G RP16E RP16C RP16A RP18F RP19E RP19C RP19A STD32E VMEM VL-486-4 Reference Manual Schematic – 107...
  • Page 120 XD15 XD15 LD15 LA11 RP2B RP3A CT16646 CT16244 LA11 U19D RP3F LA22 LA12 U17B RP3G LA10 LA13 RP12B MUX* LA23 LA14 RP12C LA15 BEN* LA16 CT16244 LA17 LA18 LA19 XA20 LA21 LA22 LA23 CT16646 108 – Schematic VL-486-4 Reference Manual...
  • Page 121 XCLK NC48 NC99 XCLK RST* FLASH29F0X0 FLASH29F0X0 NC89 NC100 GOE0 GOE0 SI16* ISPEN ISPEN ISPEN GOE1 ISPEN ISPEN SI16* SI16* SCLK LA19 SCLK/SI16 SCLK SCLK LA11 LA11 MODE MODE/LA11 MODE MODE LA19 P4864A P4864B VL-486-4 Reference Manual Schematic – 109...
  • Page 122 RP11A ZWR* ZRD* ZCE* C1MHZ PCLK FUSE CT/DIO/INT NC28 NC29 DINT* INTAK 8536 RP1F RP1G FPI3* DINT* FPI1* FPRQ* RP11E U22D FPI2* FPAK* RP11G FPWR* FPI3* FPI3 DINT FPRD* FPI2* FPI2 FPI1* FPI1 CT16240 110 – Schematic VL-486-4 Reference Manual...

  • Page 123: Index

    IBM PC/AT External Connector (J2), 50 Interrupts, 35 Interrupts, 35 Initialization Connectors. See External Connectors 486SXLC, 42 Counter/Timer 82C721, 42 External Connector (J2), 51 82C836, 41 Counter/Timers Introduction, 40 Control Registers, 64 RAM Refresh, 43 VL-486-4 Reference Manual Schematic – 111...
  • Page 124 Setup. See CMOS RAM, Setup Map and Paging Control Register, 67 Shipping, 8 Memory Slot X, 46 Description, 2 Speaker, 49 Mapping, 24 External Connector (L1), 55 Memory Map Special Control Register, 39, 65 112 – Index VL-486-4 Reference Manual...
  • Page 125 Video Adapter. See SVGA SVGA Watch Dog Timer Card Installation, 10 Description, 3 Card Placement, 46 Watchdog Installation, 11 Enable/Disable, 65 Interrupts, 35 Hold Off, 66 Termination, 27 Z8036. See CIO Timers. See Counter/Timers VL-486-4 Reference Manual Index – 113...

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