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VersaLogic VL-12CT96 Reference Manual

Analog & digital input/output card for the std 32 bus
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VL-12CT96
VL-12CT97
VL-12CT98
Analog & Digital Input/Output
Card for the STD 32 Bus

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Summary of Contents for VersaLogic VL-12CT96

  • Page 1 Reference Reference Manual Manual VL-12CT96 VL-12CT97 VL-12CT98 Analog & Digital Input/Output Card for the STD 32 Bus...
  • Page 2 VL-12CT96/7 Analog & Digital I/O Card...

  • Page 3: Table Of Contents

    VL-12CT96/7 Jumper Block Locations ........
  • Page 4 Analog Input Data High Register ......... 4-7 Analog Input Data Representation (VL-12CT96, 12-Bit) ......4-8 Analog Input Data Representation (VL-12CT97, 16-Bit) .

  • Page 5: Overview

    The VL-12CT96/7 provides 16 single-ended, or 8 differential analog input channels (12-bit resolution for the VL-12CT96 or 16-bit resolution for the VL-12CT97). Four of the input channels may optionally be configured for current loop input. The cards feature fast 10 µs conversion times, and on-board DC to DC converters (requires +5 volt supply only).

  • Page 6: Specifications

    Bus Compatibility: Bus Compatibility: Bus Compatibility: STD Z80: Full compliance, all bus speeds STD 80: Full compliance, all bus speeds STD 32: I/O slave, SA16, SA8-I, IX Specifications are subject to change without notice. VL-12CT96/7 Analog & Digital I/O Card...

  • Page 7: Configuration

    The terms “In” or “Jumpered” are used to indicate an installed plug; “Out” or “Open” are used to indicate a removed plug. Figure 2-1 shows the jumper block locations on the VL-12CT96/7 card. The figures indicate the position of the jumpers as shipped from the factory.

  • Page 8: Vl-12Ct96/7 Jumper Block Locations

    Configuration — Jumper Block Locations VL-12CT96/7 Jumper Block Locations Figure 2-1. Jumper Block Locations for VL-12CT96/7 VL-12CT96/7 Analog & Digital I/O Card...

  • Page 9: Vl-12Ct96/7 Jumper Options

    Analog Input Resolution ..........Varies 2-14 – 16-Bit Resolution (VL-12CT97 only) Out – 12-Bit Resolution (VL-12CT96 only) VL-12CT96/7 Analog & Digital I/O Card...
  • Page 10 Use STD Bus IRQ3* to carry ADC conversion complete interrupt ....Disabled 2-19 – Connects ADC interrupt circuitry to STD Bus IRQ3* (E67) Out – Frees IRQ3* to be used for other purposes Figure 2-2. VL-12CT96/7 Jumper Functions VL-12CT96/7 Analog & Digital I/O Card...

  • Page 11: Board Addressing

    Configuration — Board Addressing Board Addressing The VL-12CT96/7 card supports both 8- and 16-bit I/O addressing. 8-bit addressing is used with most 8-bit processors (Z80, 8085, 6809, etc.) which provide 256 I/O addresses. 16-bit addressing can be used with 16-bit processors (i.e. 8088, 80188, etc.) to decode up to 65536 I/O port addresses.

  • Page 12: 16-Bit Addressing

    = Out – A6 Decoded High [5-6] = In – A5 Decoded Low [5-6] = Out – A5 Decoded High [7-8] = In – A4 Decoded Low [7-8] = Out – A4 Decoded High Figure 2-4. 16-Bit Address Jumpers VL-12CT96/7 Analog & Digital I/O Card...

  • Page 13: Ioexp Signal

    STD 32 card cage. In 8-bit mode, the register map for the VL-12CT96/7 is a superset of the Analog Devices RTI-1265 board. In 16-bit mode, the registers are remapped to even addresses for efficient I/O access. This allows the full A/D data word to be read in a single bus cycle.

  • Page 14: Analog Input Configuration

    Configuration — Analog Input Analog Input Configuration The VL-12CT96/7 board accommodates 16 single-ended or 8 differential input channels. Input Mode The board can be configured for three types of analog inputs: differential, single-ended, or pseudo- differential. All inputs connected to the board must be of the same type.

  • Page 15: Pseudo-Differential Mode

    16 input channels are available in pseudo-differential mode. This mode is used when connecting to a 5B01 signal conditioning rack. VL-12CT96 VL-12CT97 CHANNEL 0 CHANNEL 1 OPTIONAL AGND P.D. SENSE Figure 2-7. Pseudo-Differential Input Mode VL-12CT96/7 Analog & Digital I/O Card...

  • Page 16: Differential Mode

    Differential Bias Resistor ..........In Circuit – In Circuit Out – Disconnected Figure 2-9. Bias Resistor 2-10 VL-12CT96/7 Analog & Digital I/O Card...

  • Page 17: Current Loop Mode

    Configuration — Analog Input Current Loop Mode In addition to voltage mode inputs, the VL-12CT96/7 can accept up to four 4-20 ma current loop inputs. Channels 0 through 3 can be converted to current-loop input by installing 200 to 250 Ω, ¼W, 0.1% precision resistors in locations R4 through R7 respectively.

  • Page 18: Input Range

    Input Range ............±10V [1-2] & [7-8] In – ±10 Volts [3-4] & [5-6] In – ±5 Volts Figure 2-11. Input Range Jumper 2-12 VL-12CT96/7 Analog & Digital I/O Card...

  • Page 19: Settling Time

    Configuration — Analog Input Settling Time The VL-12CT96/7 board inserts a short delay between the time a channel is selected and time the A/ D conversion begins. The delay allows the multiplexer and associated circuitry to properly settle for a more accurate reading.

  • Page 20: Input Resolution

    Configuration — Analog Input Input Resolution The VL-12CT96 provides 12 bits of resolution (4096 digital counts). For correct operation, jumper V8[3- 4] should be removed. The VL-12CT97 provides 16 bits of resolution (65536 counts) for applications which require finer resolution. For correct operation, jumper V8[3-4] should be inserted.

  • Page 21: Output Voltage Range

    When a load is driven over a long cable, the resistance of the wire can cause a voltage drop to occur. This can result in erroneous signal levels at the remote end of the line. The VL-12CT96/7 board can compensate for this drop (up to 3 volts of loss) by measuring the voltage at the far end of the line through a separate sense line.

  • Page 22: Output Current Loop Option

    Channel 0 can optionally be configured to produce current loop output in the range of 4 to 20 mA. Normally this is a factory installed option. Contact VersaLogic for further information. Note: When using the 4-20 mA option, channel 0 must be configured for ±10 volt output range.

  • Page 23: 5B01 Analog Signal Conditioning Rack

    I/O rack or the V5 jumper must be removed. Note that the +5 volt power output from the VL-12CT96/7 card can be shorted to ground if the connector is not correctly oriented at either end of the interface cable. The use of keys in the connectors, or very clear markings on the connectors, is recommended to prevent backwards connection of the cable.

  • Page 24: Digital I/O Interrupts

    V13[1-2] Interrupt Edge Selector ........... . Rising Edge Only – Rising Edge Only Out – Rising and Falling Edges Figure 2-22. Digital Interrupt Edge Select 2-18 VL-12CT96/7 Analog & Digital I/O Card...

  • Page 25: Interrupt Configuration

    Configuration — Interrupt Interrupt Configuration Jumpers V14 through V18 connect the interrupt request signals from the VL-12CT96/7 card to five STD Bus interrupt request lines. The choice of which jumper position to choose depends upon the capabilities of the CPU or interrupt controller used in the system.
  • Page 26 2-20 VL-12CT96/7 Analog & Digital I/O Card...

  • Page 27: Installation

    (such as the one it was received in). Installation The VL-12CT96/7 card can be installed in any slot of an STD Bus card cage, excluding Slot X in STD 32 cages.

  • Page 28: External Connections

    Installation — External Connections External Connections J1, J2 and J3 are unlatched header type connectors. External connections to the VL-12CT96/7 can be made with standard cable assemblies, or with the following mating connectors: Connector Mating Connector 26-pin socket type connectors such as 3M #3399-6626...

  • Page 29: J1 - Analog Input Connector

    The use of multiple ground connections is recommended to maintain a high degree of signal integrity. This signal is not connected to on-board circuitry. It has no function on the N/C — No Connection. VL-12CT96/7. VL-12CT96/7 Analog & Digital I/O Card...

  • Page 30: J2 - Analog Output Connector

    This signal is the on-board analog ground. All signals on J2 are referenced AGND — Analog Ground. to this signal. The use of multiple Analog Ground signals is recommended to maintain a high degree of signal integrity. VL-12CT96/7 Analog & Digital I/O Card...

  • Page 31: J3-Digital I/O Connector

    I/O rack or the V5 jumper must be removed. All signals on connector J3 are referenced to these digital ground connections. The use Digital ground. of all ground connections is recommended to maintain a high degree of signal integrity. VL-12CT96/7 Analog & Digital I/O Card...
  • Page 32 VL-12CT96/7 Analog & Digital I/O Card...

  • Page 33: Registers

    I/O Port Mapping The VL-12CT96/7 uses one of two I/O port maps depending upon whether the data bus is configured for 8-bit or 16-bit operation. In 8-bit mode, registers are mapped to correspond with Analog Device’s RTI-1265 board.

  • Page 34: Analog Input Registers

    Control Register CONTROL — 0300H Figure 4-3. Control Register The Control register is a write register used to configure the operating mode of the VL-12CT96/7. This bit has no function on the VL-12CT96/7. D7 — Not Used. These two bits define and restrict the number of channels scanned in auto- D6, D5 —...
  • Page 35 Before selecting auto-increment mode, the initial channel to be converted (usually channel 0) should be selected by writing to the SELECT register. Setting this bit to “1” places the VL-12CT96/7 in auto-trigger mode. In this D3 — Auto Trigger Enable.

  • Page 36: Channel Select Register

    A word-wide output instruction to the SELECT register (out dx,ax) also writes into the CONVERT register causing channel addressing and triggering with one CPU instruction. These bits have no function on the VL-12CT96/7. D7, D6, D5, D4 — Not Used.

  • Page 37: Convert Register

    A word-wide output instruction to the SELECT register (out dx,ax) also writes into the CONVERT register causing channel addressing and triggering with one CPU instruction. These bits have no function on the VL-12CT96/7. Any value written triggers an A/ D7-D0 — Not Used.

  • Page 38: Analog Input Read Registers

    Figure 4-9. Status Register The STATUS register is a read register which contains the status of the VL-12CT96/7. It can be read at any time to determine if an A/D conversion is complete, or if a parallel port interrupt is pending.

  • Page 39: Analog Input Data Low Register

    • The next channel in sequence is selected if auto-increment mode enabled. • A new A/D conversion is triggered if auto-trigger mode is enabled. These bits contain data bits D15 through D8 of the D7-D0 — A/D Input Data (Most Significant Byte). conversion results. VL-12CT96/7 Analog & Digital I/O Card...

  • Page 40: Analog Input Data Representation (Vl-12Ct96, 12-Bit)

    Registers — Analog Input Registers Analog Input Data Representation (VL-12CT96, 12-Bit) The VL-12CT96 converts applied analog voltages into 12-bit, two’s complement digital words. The full applied analog input range is divided into 4096 steps. The output code (0000H) is associated with a mid- range analog value of 0 Volts (ground).

  • Page 41: Analog Input Data Representation (Vl-12Ct97, 16-Bit)

    -2.500000 -0.012500 -0.025000 E000 -8192 Negative quarter scale -2.500000 -5.000000 -0.025000 -0.050000 C000 -16384 Negative half scale -5.000000 -10.000000 -0.050000 -0.010000 8000 -32768 Maximum negative voltage Figure 4-13. Two’s Complement Data Format (VL-12CT97, 16-Bit) VL-12CT96/7 Analog & Digital I/O Card...

  • Page 42: Analog Output Registers

    The analog output value changes when DACxHI is updated. See the D/A Data Low Register section for further information on register access. These bits have no function on the VL-12CT96/7. D7-D4 — Not Used. The data written to these bits forms data bits D11 D3-D0 —...

  • Page 43: Analog Output Data Representation

    Registers — Analog Output Registers Analog Output Data Representation The VL-12CT96/7 converts 12-bit, two’s complement digital words into ±5V, ±10V, or 4-20 ma output signals. The output is divided into 4096 steps. The code 0000H produces an analog output of 0 Volts (ground).

  • Page 44: Parallel Port Registers

    Parallel Port Registers Signal Direction The VL-12CT96/7 parallel port signals are bidirectional. When the system is powered up, or a system reset occurs, all of the channels are reset to inputs which causes the signal lines to go high. Channels can be used as outputs by writing 0 or 1 to the appropriate bit in the PARHI or PARLO register.
  • Page 45 Operation Operation This section describes how to operate the VL-12CT96/7. Analog input, analog output, and digital I/O are discussed. Code examples written in 80188 assembly language are included in the next section. Analog Input Polled Mode Analog Input Polled mode operation is the simplest method of analog input. In this mode, software is in control of the analog input process at all times.

  • Page 46: Operation Analog Input

    Interrupt mode eliminates the need to repeatedly poll the STATUS register for Done status. This frees up the CPU to execute unrelated code while the VL-12CT96/7 is busy with an A/D conversion. This is especially useful when using long settling delays. Another use for interrupts is for handling auto triggered applications.

  • Page 47: Analog Output

    7 completes an A/D conversion. Analog Output Writing to a VL-12CT96/7 analog output channel is as simple as writing 12 bits of data to the desired output registers. Each channel has two registers, DACxLO and DACxHI. DACxLO should be written to first, followed by DACxHI.

  • Page 48: Signal Inversion

    Signal Inversion All parallel port circuits on the VL-12CT96/7 board are inverting. A high logic level on connector J3 is represented by a 0 in the PARLO or PARHI register, and a low logic level is represented by a 1.

  • Page 49: Software Examples

    This section shows some software examples written in Intel compatible assembly language to assist you in constructing your own software routines. The interrupt code examples are written specifically for use with VersaLogic’s 80188 CPU card, VL-188. Analog Input Code Example The following example reads channel 0 into the AX register.

  • Page 50: Analog Input Interrupt Mode Code Example

    Initializes the VL-188 interrupt controller to accept interrupts from the STD INIT_188 : Bus. Installs interrupt vector into low RAM. Initializes the VL-12CT96/7 to generate interrupts upon conversion complete. INIT_1296 : Interrupt Service Routine. This subroutine is responsible for reading, process- ISR : ing, and/or storing the A/D results from the VL-12CT96/7.
  • Page 51 ;Additional processing code is ;inserted here if desired. ;This could include mathematic ;manipulation, data storage, ;limit checks, etc. 004F isr_exit: 004F BA FF22 dx,eoi ;Issue a Non-Specific End-Of-Interrupt 0052 B8 8000 ax,8000h ;command to 80188 interrupt controller VL-12CT96/7 Analog & Digital I/O Card...

  • Page 52: Analog Output Code Example

    ;OUTPUT ZERO VOLTS ON CHANNEL 0 0000 BA 030C dx,dac0lo ;Select channel 0 0003 B8 0000 ax,0000h ;0000h = Zero volts in 2’s complement mode 0006 dx,ax ;Output data to D/A converter write VL-12CT96/7 Analog & Digital I/O Card...

  • Page 53: Parallel Port Code Example

    1 MD13 Direction = Output 1 MD14 Direction = Output 1 MD15 Direction = Output 000B B0 0F al,15 ;Turn MD15 ON 000D E8 0031 call channel_on 0010 B0 0F al,15 ;Turn MD15 OFF VL-12CT96/7 Analog & Digital I/O Card...
  • Page 54 ;AL=Channel Number. If an input ;channel is specified, nothing ;happens. 0041 push 0042 push 0043 push 0044 BB 8000 bx,8000h ;Setup initial mask position 0047 8A C8 cl,al ;Use channel # as rotate counter VL-12CT96/7 Analog & Digital I/O Card...
  • Page 55 0067 ax,dx 0068 23 C3 ax,bx ;Clear bit to turn channel on 006A 23 06 0000r ax,dir ;Clear bits associated with input 006E dx,al ;Update parallel port 006F ;Restore registers 0070 0071 0072 main VL-12CT96/7 Analog & Digital I/O Card...

  • Page 56: Parallel Port Interrupt Mode Code Example

    Defines the signal direction of the parallel port channels. All output channels INIT_PAR : are turned off. Interrupt Service Routine. This subroutine is responsible for reading, and ISR : processing the parallel port input from the VL-12CT96/7. 0000 .model small 0000 .stack 0000 .data...
  • Page 57 ;Turns all output channels off 0039 push 003A A3 0000r dir,ax ;Save pattern to guarantee we never ;output a “1” to an input channel 003D B8 0000 ax,0000h ;Turn all output channels off 0040 BA 030A dx,parlo VL-12CT96/7 Analog & Digital I/O Card...
  • Page 58 0052 BA FF22 dx,eoi ;Issue a Non-Specific End-Of-Interrupt 0055 B8 8000 ax,8000h ;command to 80188 interrupt controller 0058 dx,ax 0059 ;Restore CPU registers 005A 005B 005C iret ;Return to interrupted program main 6-10 VL-12CT96/7 Analog & Digital I/O Card...

  • Page 59: Calibration

    Calibration Calibration The VL-12CT96/7 is calibrated before shipment. However, it may be desirable to recalibrate the card after installation, and approximately once per year (depending upon the accuracy requirements of the application). Analog Input Calibration Required Equipment • A voltmeter with resolution and accuracy to ½ LSB of the input range being used.

  • Page 60: Analog Output Calibration (Voltage Mode)

    • Adjust Z1 pot until voltage is exactly -10.0000V. • Write 07FFH to channel 1. • If using ±5V range, adjust G1 pot until voltage is exactly +4.997559V. If using ±10V range, adjust G1 pot until voltage is exactly +9.995117V. VL-12CT96/7 Analog & Digital I/O Card...

  • Page 61: Analog Output Calibration (Current Mode)

    • Calculate C= A–B–12 • Turn Z0 pot counterclockwise until the current flow equals “C” milliamps. • Write 07FFH to channel 0. • Turn G0 pot counterclockwise until the current flow equals 20.0000 milliamps. VL-12CT96/7 Analog & Digital I/O Card...
  • Page 62 VL-12CT96/7 Analog & Digital I/O Card...

  • Page 63: Reference

    AUX Ground AUX +V — AUX Positive (+12VDC) AUX -V — AUX Negative (-12VDC) * Denotes an active low signal. — Denotes signal not used on this board. Figure 8-1. STD 80 Bus Pinout VL-12CT96/7 Analog & Digital I/O Card...

  • Page 64: Std 32 Bus Pinout Extension

    Address XA25* — Address XA29* — Address XA24* — Address XA28* — Address * Denotes an active low signal. — Denotes signal not used on this board. Figure 8-2. STD 32 Bus Pinout Extension VL-12CT96/7 Analog & Digital I/O Card...

  • Page 65: Vl-12Ct96/7 Parts Placement

    Reference VL-12CT96/7 Parts Placement VL-12CT96/7 Analog & Digital I/O Card...

  • Page 66: Vl-12Ct96/7 Schematic

    Reference VL-12CT96/7 Schematic +12V -12V STD32P STD32E 07/12/93 Rev2 VL-12CT96/7 Analog & Digital I/O Card...
  • Page 67 BD14 MA2_LO RP13A XX245 XX245 BD15 XX174 MA3_LO D[0..7] BRST* BRST* HI_EN* BD[0..15] +15V RP13B RP13C AGND RP13D BD10 RP13E BD11 HPR105 -15V RP13F BD12 RP13G BD13 RP14A BD14 RP14B XX245 BD15 07/12/93 Rev2 VL-12CT96/7 Analog & Digital I/O Card...
  • Page 68 AD_HI* L_CNVT BUSY* AD_HI* ATR_EN DONE* AD_LO* AD_LO* DONE* CNVT* XX74 XX74 R/C* L_CLR* CLR* TRIG* +15V D_CLR* SCNVT* M+15V AD_HI* +15V M_DLY* BD11 AGND DA_D11* M-15V P1296E -15V RST* BRST* 07/12/93 Rev2 -15V VL-12CT96/7 Analog & Digital I/O Card...
  • Page 69 MD15* MD3* MD3* XX240 MD12* BD11 XX240 MD4* XX126 MO14 MO15 P_RD* P_RD* MD[0..15]* U21B U29B MD11* BD12 MD3* MD10* BD13 MD2* MD9* BD14 MD1* XX240 MD8* BD15 XX240 MD0* 07/12/93 Rev2 P_RD* P_RD* VL-12CT96/7 Analog & Digital I/O Card...

  • Page 70: Vl-12Ct96/7 Parts List

    ADS7805BP (VL-12CT97 only) REF102AP DAC7802KP U16, U17, U23, U24 74HCT257 74HCT174 74HCT221 74HCT373 U21, U29 74ACT240 U30, U22 74ACT273 PEEL18CV8-25 IP1296D Rev. 1.00 U26, U34 74HCT688 PEEL18CV8-25 IP1296E Rev. 1.00 GAL16V8A-25Q IP1296C Rev. 1.00 VL-12CT96/7 Analog & Digital I/O Card...
  • Page 71 10K Ω, 5 resistor SIP RP16 500 Ω trim pot, 15-turn VR1, VR3 100K Ω trim pot, 25-turn VR2, VR4 50K Ω trim pot, 15-turn 10K Ω trim pot, 15-turn Semiconductors 1N4148 (optional) D2, D3 1N4148 VP0300M (optional) VL-12CT96/7 Analog & Digital I/O Card...

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