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Summary of Contents for VersaLogic VL-MPEe-U2
- Page 1 Reference Manual REV. February 2021 VL-MPEe-U2 MiniPCIe Quad Serial Interface Module with GPIO...
- Page 2 Copyright © 2013-2021 VersaLogic Corp. All rights reserved. Notice: Although every effort has been made to ensure this document is error-free, VersaLogic makes no representations or warranties with respect to this product and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose.
- Page 3 BIOS and PLD information and upgrades Customer Support If you are unable to solve a problem after reading this manual, visiting the product page, or contact VersaLogic Technical Support at (503) 747-2261. VersaLogic support engineers are also available via e- mail at Support@VersaLogic.com. Repair Service If your product requires service, you must obtain a Returned Material Authorization (RMA) number by calling (503) 747-2261.
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Page 4: Table Of Contents
Handling Care ......................7 Physical Details ......................8 Board Layout and Mounting ....................8 VL-MPEe-U2 Mounting ..................8 VL-MPEe-U2 Dimensions and Connectors ............8 VL-CBR-2004B Dimensions and Connectors ............9 Jumper Blocks ........................10 VL-MPEe-U2 Jumpers As-shipped Configuration ..........10 Jumper Summary .................... -
Page 5: Introduction
I/O connectors. VL-MPEe-U2 boards are subjected to 100% functional testing and are backed by a limited two- year warranty. Careful parts sourcing and US-based technical support ensure the highest possible quality, reliability, service, and product longevity for this exceptional board. -
Page 6: Block Diagram
(PBDE) flame retardants, in certain electrical and electronic products sold in the European Union (EU) beginning July 1, 2006. VersaLogic Corp. is committed to supporting customers with high-quality products and services meeting the European Union’s RoHS directive. -
Page 7: Handling Care
Introduction After removing the board from its protective wrapper, place the board on a grounded, static-free surface, component side up. Use an antistatic foam pad if available. The board should also be protected inside a closed metallic antistatic envelope during shipment or storage. Note: The exterior coating on some metallic antistatic bags is sufficiently conductive to cause excessive battery drain if the bag comes in contact with the bottom side of... -
Page 8: Physical Details
-U2 M OUNTING The VL-MPEe-U2 is a full size Mini PCIe card and needs to be mounted into a full size Mini PCIe site. On VersaLogic CPU boards, the module is secured using two nylon screws. VersaLogic offers 2 mm nylon screws (VL-HDW-110) and 2.5 mm nylon screws (VL-HDW- 108). -
Page 9: Vl-Cbr-2004B Dimensions And Connectors
Physical Details Table 1 provides information about the function, mating connectors, and transition cables for VL-MPEe-U2 connectors. Page numbers indicate where a detailed pinout or further information is available. Table 1: Connector Functions and Interface Cables Mating Transition Cable Connector... -
Page 10: Jumper Blocks
12” latching receptacle cable to VL-CBR-2004B I/O board Jumper Blocks VL-MPE -U2 J UMPERS SHIPPED ONFIGURATION All jumpers on the VL-MPEe-U2 are shipped in the out (or "storage") position, as shown in the figure below. Figure 3. VL-MPEe-U2 Jumper As-shipped Configuration... -
Page 11: Jumper Summary
Physical Details UMPER UMMARY Table 3: Jumper Summary Jumper Block Description Shipped V1[1-2] COM1 RS-422 Rx or RS-485 Termination In – 120 Ohm terminated Out – Not terminated V1[3-4] COM2 RS-422 Rx or RS-485 Termination In – 120 Ohm terminated Out –... -
Page 12: Interfaces And Connectors
Interfaces and Connectors Serial Ports The VL-MPEe-U2 features four on-board 16550-based serial channels. All four channels are 4-wire RS-232/RS-422/RS-485 ports with baud rates up to 400 Kbps. Connector J1 provides an interface to the COM1 and COM2 ports. Connector J2 provides an interface to the COM3 and COM4 ports. -
Page 13: Serial Port Connectors
The following tables show the function of each pin of the J1 and J2 connectors, and how the signals are routed to the DB9 connectors on the VL-CBR-1014 cable. Table 4: J1 Serial Port Connector Pinout VL-MPEe-U2 VL-CBR-1014 Signal J1 Pin... -
Page 14: General Purpose I/O (Gpio) Lines
GPIO outputs can be set to be normal HIGH or LOW state, or open drain. There are 10K pull-up resistors to +3.3V on all GPIO lines. VersaLogic provides a set of API calls for managing the GPIO lines. See Application Programming Interface (API) for information. -
Page 15: Leds
Interfaces and Connectors Table 7 shows how the GPIO signals are routed to the VL-CBR-2004B paddleboard screw terminals. Table 7: VL-CBR-2004B Terminal Block Pinouts VL-CBR-2004B J1 Pin Signal Name Function DGND1 Ground DIO1 GPIO0 DIO2 GPIO1 DGND1 Ground DIO3 GPIO2 J2 Pin DIO4 GPIO3... -
Page 16: Application Programming Interface (Api)
Outputs: unsigned long This call returns 0 if the open was a success and nonzero if no useable drivers were found by the DLL. For the VL-MPEe-U2, the useable driver is the Exar serial port driver. VSL_Close(); Closes the VersaAPI library. -
Page 17: Digital I/O (Dio) Calls
Application Programming Interface (API) VSL_GetVersion() Gets the version number of the VersaAPI library Syntax: VL_OSALIB_API void VSL_GetVersion(unsigned char *Major, unsigned char *Minor, unsigned char *Revision); Inputs: unsigned char *Major A pointer to the unsigned character to receive the Version Major number. unsigned char *Minor A pointer to the unsigned character to receive the Version Minor number. - Page 18 Application Programming Interface (API) VSL_DIOGetChannelLevel Reads the signal level of the specified channel. Syntax: VL_OSALIB_API unsigned char VSL_DIOGetChannelLevel(unsigned char Channel); Inputs: unsigned char Channel The DIO channel number to be interrogated. Outputs: unsigned char Returns the state of the channel as either high (DIO_CHANNEL_HIGH) or low (DIO_CHANNEL_LOW).
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