VersaLogic VL-486-4 Manuals

Manuals and User Guides for VersaLogic VL-486-4. We have 1 VersaLogic VL-486-4 manual available for free PDF download: Reference Manual

VersaLogic VL-486-4 Reference Manual

VersaLogic VL-486-4 Reference Manual (125 pages)

Industrial CPU Card for the STD 32 Bus

Brand: VersaLogic | Category: Computer Hardware | Size: 0 MB

Table of Contents

Table of Contents
7
Other References
11
1 Overview

13
- Using this Manual
  13
- Introduction
  13
  - PC/AT Compatibility
    13
  - STD BUS Compatibility
    13
  - On-Board Memory
    14
  - Hard Disk and Floppy Disk Interface
    14
  - Digital I/O (Opto 22) Interface
    14
  - COM Ports
    14
  - Parallel Port
    14
  - Counters/Timers
    14
  - Real Time Clock with CMOS RAM
    15
  - Interrupt Controllers
    15
  - DMA Controllers
    15
  - Watchdog Timer
    15
- Technical Specifications
  16
- Technical Support
  17
2 DOS Based Quick Start

19
- Introduction
  19
- Installation
  20
- Activating the Battery
  20
- Jumper Locations
  21
- Card Installation
  22
- Monitor and Keyboard Installation
  23
- Cable Installation
  24
- CMOS RAM Setup
  24
- CMOS Setup Options
  25
  - Main CMOS Setup Menu
    25
  - Basic CMOS Configuration
    25
  - Advanced CMOS Configuration
    25
  - Reset CMOS to Last Known Values
    25
  - Reset CMOS to Factory Defaults
    26
  - Write to CMOS and Exit
    26
  - Exit Without Changing CMOS
    26
- Clearing the CMOS RAM
  27
3 Configuration

29
- Hardware Jumper Summary
  29
  - Jumper Block Locations
    30
- Memory Configuration
  33
  - ROM Configuration
    33
  - Compatible ROM Devices
    33
  - RAM Configuration
    34
  - Compatible RAM Devices
    34
  - CMOS RAM Configuration
    35
  - Memory Mapping
    36
- I/O Configuration
  37
  - Using 8-Bit I/O Cards
    37
  - Using 10-Bit I/O Cards
    37
  - Using 16-Bit I/O Cards
    38
- COM2 Configuration
  39
  - Operation
    39
- Opto 22 Rack Configuration
  41
  - Rack Power Control
    41
- Multiprocessor Configuration
  42
- Interrupt Configuration
  44
- DMA Configuration
  50
- DMA Channel Allocation
  51
- Board Initialization
  52
  - 82C836 Initialization
    53
  - 82C721 Initialization
    54
  - 486SXLC Initialization
    54
  - RAM Refresh Initialization
    55
4 Installation

57
- Introduction
  57
- Activating the Battery
  57
- Card Insertion and Extraction
  57
  - Card Installation
    58
  - Card Placement
    58
  - STD 32 Bus Installation Guidelines
    58
- External Connections
  59
5 Register Descriptions

69
- Introduction
  69
- Register Summary
  69
  - Direct Memory Access - Channel 1
    70
  - Direct Memory Access - Channel 2
    71
  - Direct Memory Access
    71
  - COM1 Serial Port
    72
  - COM2 Serial Port
    72
  - LPT1 Parallel Port
    73
  - Chipset Registers
    73
  - Floppy Disk Drive Controller
    74
  - IDE Hard Disk Drive Controller
    74
  - Interrupt Controller - Master
    75
  - Interrupt Controller - Slave
    75
  - Counter/Timers
    76
  - Miscellaneous
    76
  - CIO Chip
    76
  - Special Control Register
    77
  - Watchdog Timer Hold-Off Register
    78
  - Map and Paging Control Register
    79
6 CIO Chip

81
- Introduction
  81
  - Features
    82
  - Overview
    82
  - I/O Ports
    82
  - Ports Aandb
    82
  - Portc
    83
  - Counter/Timers
    83
  - Interrupt Control Logic
    83
- Register Description
  83
  - Introduction
    83
  - CIO Registers
    84
  - Register Access
    85
  - State 0
    85
  - State 1
    85
- Master Control Registers
  86
- Port Handshake Specification Registers
  91
  - Port A/B Handshake Specification Registers
    91
  - Port Command and Status Registers
    91
- Bit Path Definition Registers
  93
- Pattern Definition Registers
  95
- Interrupt Related Registers
  102
  - Interrupt Vector Registers
    102
  - Current Vector Register
    103
- I/O Port Operation
  104
  - Overview
    104
  - Pattern-Recognition Logic Operation
    104
  - Bit Port Operation
    104
  - Bit Port Simple Operation
    104
  - Bit Port Pattern-Recognition Operation
    105
- Counter/Timer Operation
  106
  - Counter/Timer Architecture
    106
  - Counter/Timer Sequence of Events
    107
  - Initializing the Counter/Timer
    107
  - Starting the Counter/Timer
    108
  - Countdown Sequence
    108
  - Ending Condition
    109
  - Counter/Timer Output
    110
  - Linked Sequence
    110
- Interrupt Operation
  111
  - Overview
    111
  - Priority Handling and the CIO
    111
  - The Four Interrupt Logic Functions
    111
  - Generating the Interrupt Request
    111
  - Identification of the Highest-Priority Interrupt Request
    112
  - Interrupt Operation
    113
- CIO Initialization
  113
  - Introduction
    113
  - Enable Bits Operation
    114
- Programming
  114
  - Interrupt Code Example
    115
Appendix A - Schematic

119
Index

123

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