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VersaLogic VL-586-1kn Reference Manual

5x86 industrial cpu card for the std 32 bus
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VL-586-1
5x86 Industrial CPU Card
for the STD 32 Bus
TM

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  • Page 1 Reference Reference Reference Reference Manual Manual Manual Manual VL-586-1 5x86 Industrial CPU Card for the STD 32 Bus...
  • Page 3 VL-586-1 5x86 Industrial CPU Card for the STD 32 Bus M586-1...
  • Page 5 All Rights Reserved Notice: Although every effort has been made to ensure this document is error-free, VersaLogic makes no representations or warranties with respect to this product and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose.

  • Page 7: Table Of Contents

    Table of Contents Other References ....................... vi 1. Overview ........................1 Using This Manual ......................1 Introduction ........................1 PC/AT Compatibility..................... 1 STD/STD32 Bus Compatibility................2 PC/104-Plus Compatibility ................... 2 On-Board Memory ....................2 Hard Disk and Floppy Disk Interface..............2 Serial Ports......................
  • Page 8 Table of Contents Memory Configuration ..................... 22 ROM Configuration..................... 22 DRAM Configuration..................22 CMOS RAM Configuration ................23 Battery Backed SRAM Configuration..............23 Memory Map ....................... 24 I/O Configuration ......................25 Using 8-Bit STD Bus I/O Cards ................25 Using 10-Bit STD Bus I/O Cards ................ 25 Using 16-Bit STD Bus I/O Cards ................
  • Page 9 Table of Contents 5. Register Descriptions .....................51 Introduction ........................51 Register Summary ......................51 Direct Memory Access — Channel 1..............52 Direct Memory Access — Channel 2..............53 Direct Memory Access — Page Registers ............53 COM1 Serial Port ....................54 COM2 Serial Port ....................

  • Page 10: Other References

    Other References Other References Acer Laboratories Inc., (408) 764-0644, http://www.ali.com.tw M1489 / M1487 486 PCI Chipset Data Book Chips and Technologies, Inc., (408) 434-0600, http://www.chips.com 82C735 Super I/O Chip Data Book STD 32 Manufacturers Group, (800) 733-2111, http://www.std32.com STD 32 Bus Specification and Designer’s Guide Advanced Micro Devices (800) 222-9323, http://www.amd.com AM486DX5-133V17BHC Data Book Additional Resources,...

  • Page 11: Overview

    Overview Using This Manual Each chapter in this manual corresponds to a step in the installation process: Chapter 1 – Overview Lists basic information about the CPU card, specifications, and system requirements. Use this chapter to familiarize yourself with the card and it’s capabilities. Chapter 2 –...

  • Page 12: Std/Std32 Bus Compatibility

    Introduction STD/STD32 B OMPATIBILITY The VL-586-1 CPU card complies with certain subsets of the STD 32 Bus specification that allow it to communicate with STD 80 compatible 8-bit and STD 32 compatible 16-bit I/O and memory cards. In addition, the card fully complies with the STD 80 Bus specification using a bus speed of 8.33 MHz.

  • Page 13: Parallel Port

    Introduction ARALLEL The parallel port can be used as a standard bi-directional/ECP/EPP compatible LPT port or as 17 general purpose TTL I/O signals. When operating in standard bi-directional mode, each output line has a 24 ma current sink rating. Eight of the signals are programmable as a group for input or output, three are dedicated output, and five are dedicated inputs.

  • Page 14: Technical Specifications

    Technical Specifications Technical Specifications Specifications are typical at 25°C with 5.0V supply unless otherwise noted. Size: Meets all STD 80 and STD 32 Bus mechanical specifications Storage Temperature: -40 °C to 85 °C Free Air Operating Temperature: 0 °C to 65 °C Power Requirements: (with 8 MB DRAM, 512 K Flash, 512 K SRAM, Keyboard) 5V ±5% @ 1570 ma...

  • Page 15: Technical Support

    Technical Support Technical Support If you have problems that this manual can’t help you solve, contact VersaLogic for technical support at (800) 824-3163 or (541) 485-8575. You can also reach VersaLogic by e-mail at info@versalogic.com. EPAIR ERVICE If your product requires service, you must obtain a Returned Material Authorization (RMA) number by calling (800) 824-3163.

  • Page 17: Dos Based Quick Start

    DOS Based Quick Start This chapter describes how to quickly get your DOS-based system set up and running using the VL-586-1 CPU card Introduction A minimum DOS based run time system requires the CPU card, a BIOS, and a boot device containing an operating system and an application program.

  • Page 18: Installation

    Installation Installation Caution Electrostatic discharge (ESD) can damage cards, disk drives, and other components. Do the installation procedures described in this chapter only at an ESD workstation. If such a station is not available, you can provide some ESD protection by wearing an antistatic wrist strap and attaching it to a metal part on the card cage.

  • Page 19: Jumper Locations

    Jumper Locations Jumper Locations Note Jumpers and resistor packs shown in as-shipped configuration. Figure 1. VL-586-1 CPU Card Layout VL-586-1 Reference Manual DOS Based Quick Start – 9...

  • Page 20: Card Installation

    Card Installation Card Installation A typical development system consists of a six-slot V32-06T Card Cage, populated with: • VL-586-1 CPU Card (with attached EPM-SVGA PC/104-Plus Video Module) • IDE Hard Disk Drive • Floppy Disk Drive A VGA compatible monitor and a PC/AT compatible keyboard are also required to complete the set of hardware necessary for development purposes.

  • Page 21: Monitor Installation

    Monitor Installation Monitor Installation A VGA monitor should be connected to the EPM-SVGA module as shown . Figure 2. Jumpers/Connections for an EPM-SVGA Using a VGA Monitor VL-586-1 Reference Manual DOS Based Quick Start – 11...

  • Page 22: Cable Installation

    Cable Installation To bring the header connectors on the VL-586-1 CPU card out to industry standard PC pinouts, the VersaLogic cable VL-CBL-100A is used. CMOS RAM Setup The VL-586-1 CPU card uses battery-backed, non-volatile CMOS RAM provided by the real time clock chip to store system configuration settings.

  • Page 23: Cmos Setup Options

    CMOS Setup Options CMOS Setup Options CMOS S ETUP SYSTEM BIOS SETUP - UTILITY VERSION 2.001.xxx (C) 1994-1996 VERSALOGIC, CORP. ALL RIGHTS RESERVED Basic CMOS Configuration Advanced Configuration Shadow Configuration Format Integrated Flash Disk Reset CMOS to last known values...

  • Page 24: Reset Cmos To Factory Defaults

    CMOS Setup Options CMOS ESET ACTORY EFAULTS This option overwrites all information contained in the CMOS RAM with predefined parameters stored in the BIOS ROM, and reboots the CPU card. The following parameters are loaded into CMOS RAM when this option is selected: Basic CMOS Configuration +---------------------------------------+--------------------------------------+ | Base Memory...

  • Page 25: Clearing The Cmos Ram

    Clearing the CMOS RAM Clearing the CMOS RAM Jumper V6[1-2] allows you clear the CMOS RAM contents if you remove the battery, install incorrect setup information, or otherwise corrupt CMOS RAM. To ensure integrity of the CMOS RAM, the Setup program calculates and stores an internal checksum of the setup data. Upon reset, the CPU detects if the CMOS RAM is corrupted by analyzing the checksum.

  • Page 27: Configuration

    Configuration This chapter describes how to configure the on-board options for the VL-586-1 CPU card. Configuration involves both hardware (jumper) and software (CMOS Setup) configuration. The jumpers configure the circuitry on the card for various modes of operation. The CMOS Setup configuration completes the process by establishing default operating conditions.

  • Page 28: Jumper Block Locations

    Hardware Jumper Summary UMPER LOCK OCATIONS Note Jumpers and resistor packs shown in as-shipped configuration. Figure 5. Jumper Block Locations 18 – Configuration VL-586-1 Reference Manual...
  • Page 29 Hardware Jumper Summary Table 1: Jumper Summary Jumper Block Description Shipped Page V1[1-2] RS-232 Signal Enable — RS-232 mode. Enables the RS-232 line drivers and receivers. — RS-422/485 mode. Disables the RS-232 line drivers and receivers. V1[3-4] RS-422/485 Ground Circuit —...
  • Page 30 Hardware Jumper Summary Table 2: Jumper Summary (Cont.) Jumper Description Block Shipped Page V10[1-2] SO DIMM Supply Voltage (5 Volts) — Connects 5 Volts to SO DIMM Socket — Disconnects 5 Volts from SO DIMM Socket V10[2-3] SO DIMM Supply Voltage (3.3 Volts) —...
  • Page 31 Hardware Jumper Summary Table 3: Jumper Summary (Cont.) Jumper Description Block Shipped Page V18[1-2] CPU response to SYSRESET* — CPU resets whenever STD Bus SYSRESET* (P47) goes low — CPU ignores activity on STD Bus SYSRESET* (P47) V18[3-4] Push-button Reset / Bus Interconnect —...

  • Page 32: Memory Configuration

    ONFIGURATION The VL-586-1 on-board ROM socket (U3) accepts 128Kx8 or 512Kx8, 32 pin plastic or 32 PLCC pin J-lead ceramic part(s). An extractor tool (such as VersaLogic part number VL-HDW-202) is required to remove the rectangular device without damage. PLCC The VL-586-1 is sold with two ROM options: BIOS/Flash Option (-h) —...

  • Page 33: Cmos Ram Configuration

    Memory Configuration CMOS RAM C ONFIGURATION Jumper V6[1-2] (top position) can be briefly used to erase the contents of the CMOS RAM should it become necessary to do so. Table 5: CMOS RAM Jumpers Jumper Block Description Shipped V6[1-2] CMOS RAM Erase —...

  • Page 34: Memory Map

    Memory Configuration EMORY The lower 1 Meg. memory map of the CPU is arranged as follows. The upper 64K of Flash is write protected, and contains the system BIOS. It always appears from 0F0000h to 0FFFFFh. Bits D4–D0 in the MPCR register select which Flash ROM page is mapped into the 64K Page Frame (0E0000h to 0EFFFFh).

  • Page 35: I/O Configuration

    I/O Configuration I/O Configuration In addition to on-board I/O devices, the VL-586-1 also supports STD/STD 32 Bus I/O cards and PC/104 (and PC/104-Plus) modules. The total I/O space of the CPU card is 64K. The actual I/O map of the system is defined by the fixed addresses of the on-board devices in conjunction with the addresses used by external STD Bus and PC/104 modules.

  • Page 36: Using 16-Bit Std Bus I/O Cards

    I/O Configuration 16-B STD B I/O C SING ARDS STD Bus I/O cards which decode all 16 address bits (A0 - A15) will work properly with the VL- 586-1 when addressed in the following I/O ranges: • − 16Fh 0100h IOMAP2 Bit must = 1.

  • Page 37: I/O Map

    I/O Configuration I/O M Various regions of the 64K I/O space are divided up and can be routed to either the PC/104 or the STD/STD 32 bus interfaces. The IOMAP1 and IOMAP2 bits in the IOMMAP Register (see page 61) control the routing of these areas. The control bits default to values established in the CMOS Setup Advanced Configuration screen, however, they can also be manipulated in real time under program control.

  • Page 38: Com2 Configuration

    COM2 Configuration COM2 Configuration Serial Port COM2 can be operated in RS-232, RS-422, or RS-485 modes. Jumper V1 is used to configure the port. RS-232 O PERATION For RS-232 operation, jumper V1 should be jumpered as shown. The state of jumper V1[9-10] doesn't matter, it can be in or out.
  • Page 39 COM2 Configuration Table 7: Serial Port Jumpers Jumper Block Description Shipped V1[1-2] RS-232 Signal Enable — RS-232 mode. Enables the RS-232 line drivers and receivers. — RS-422/485 mode. Disables the RS-232 line drivers and receivers. V1[3-4] RS-422/485 Ground Circuit — RS-422/485 mode. Connects ground to J1 pin 6A. —...

  • Page 40: Multiprocessor Configuration

    Multiprocessor Configuration Multiprocessor Configuration The VL-586-1 CPU card supports multiple master operation for systems requiring additional processing capability or for “smart I/O” operations. In a multiple master system, one CPU must be configured as a permanent master and other CPUs are configured as temporary masters. In this scheme, a bus arbiter plugged into Slot X is used to arbitrate access to the bus.

  • Page 41: Resistor Pack Configuration

    Multiprocessor Configuration ESISTOR ONFIGURATION The eight resistor packs (RP13 through RP20) near the STD Bus connector must be removed for temporary master or dualmaster operation. Only one CPU in the card cage should have the resistor packs installed; the permanent master. Note Two resistance values are used, 1.8KΩ...

  • Page 42: Interrupt Configuration

    Interrupt Configuration Interrupt Configuration Seven three-position jumper blocks are used to configure the interrupt sources on the VL-586-1. Each jumper block is used to select one of two interrupt sources and route it to the interrupt controller. Wire wrap techniques can be used to route interrupt sources to the CPU’s IRQ inputs if the factory provided jumpers do not provide suitable connections.

  • Page 43: Interrupt Configuration Jumpers

    Interrupt Configuration NTERRUPT ONFIGURATION UMPERS Table 9: Interrupt Configuration Jumpers Jumper Block Description Shipped V11[1-2] Interrupt Configuration (IRQ3 / COM2 interconnect) — Connects COM2 to IRQ3 — Disconnects COM2 from IRQ3 V11[2-3] Interrupt Configuration (IRQ3 / INTRQ* interconnect) — Connects STD Bus INTRQ* (P44) to IRQ3 —...

  • Page 44: Std Bus Interrupt Signals

    Interrupt Configuration STD B NTERRUPT IGNALS The following table describes the six STD Bus interrupt signals. Some of these interrupt signals are hardwired to specific IRQ inputs, and others are connected to jumpers for custom configuration. Table 10: STD 32 Interrupt Signals. STD-32 STD-32 Typical...

  • Page 45: Cpu Interrupt Request Inputs

    Interrupt Configuration CPU I NTERRUPT EQUEST NPUTS The seventeen standard IBM compatible interrupt inputs (IRQs) are shown below. Table 11: Interrupt Request Inputs Interrupt Typical Source Signal Interrupt of Interrupt on As Shipped Name Number an IBM AT Configuration Notes —...
  • Page 46 Interrupt Configuration Table 11: Interrupt Request Inputs Interrupt Typical Source Signal Interrupt of Interrupt on As Shipped Name Number an IBM AT Configuration Notes IRQ8 Real Time Hardwired Internal signal, not available to Clock the outside world. Can be used for alarms or periodic interrupts.

  • Page 47: Interprocessor Communications Interrupt Configuration

    Interrupt Configuration NTERPROCESSOR OMMUNICATIONS NTERRUPT ONFIGURATION Jumpers V17[1-2] and V17[2-3] are used to route the Interprocessor Communications (IPC) interrupt signal. Two choices are available: IPC can be carried on the STD Bus signal INTRQ* (P44) or INTRQ4* (P05). If IPC is not being used, both jumpers can be removed to free up INTRQ* and INTRQ4* for other purposes.

  • Page 49: Installation

    Installation Introduction Before installing the CPU card in a card cage, you must confirm that the on-board battery is activated. Caution Electrostatic discharge (ESD) can damage cards, disk drives, and other components. Do the installation procedures described in this chapter only at an ESD workstation.

  • Page 50: Card Insertion And Extraction

    NSTALLATION UIDELINES An 8-bit STD 80 card cage (like VersaLogic's VX-Series) can be used if cost savings are a prime consideration over performance, however, the use of 8-bit cages greater than six slots is not recommended due to the high performance bus drivers used on the VL-586-1. An 8-bit STD Bus card cage may be a good choice in small embedded control systems, especially if all I/O cards are 8-bit STD 80 Bus cards, or if the system is a single-board (CPU only) design.

  • Page 51: External Connections

    External Connections External Connections This chapter describes the external interfaces available on the VL-586-1 CPU card. ONNECTOR UNCTIONS Table 14: Connector Functions Connector Function High Density I/O Connector Front Plane Interrupt Connector Floppy Drive Connector Speaker Connector ONNECTOR OCATIONS Figure 8. Connector Locations VL-586-1 Reference Manual Installation –...

  • Page 52: High Density 100-Pin Connector

    External Connections 100-P ENSITY ONNECTOR The high density 100-pin connector is brought out to standard PC connectors by cable assembly VL-CBL-100A. This chart shows the pinout for the cable assembly. Table 15: J1 High Density 100-Pin Connector Pinout External External Connector Signal Connector...

  • Page 53: Ja, Je - Serial Port Connectors

    External Connections JA, JE – S ERIAL ONNECTORS Connectors JA (COM2) and JE (COM1) provide signals for two serial I/O ports. COM1 supports RS-232 operation only, and COM2 operates in RS-232, RS-422, or RS-485 mode. Table 16: JA, JE RS-232 Serial Port Connector Pinout DB 9-Pin Male JA, JE Signal...

  • Page 54: Jb - Lpt1 Parallel Port Connector

    External Connections JB – LPT1 P ARALLEL ONNECTOR The bi-directional parallel port at JB can be used as a standard PC compatible LPT1 port or as 17 general purpose TTL I/O signals. Table 18: Parallel Port Pinout LPT1 DB 25-Pin Female Signal Centronics Signal...

  • Page 55: Jc - Counter/Timer

    External Connections JC – C OUNTER IMER External access to a variety of Counter/Timer signals is available through connector JC. Table 19: Counter/Timer Connector Pinout 14-Pin Female IDC Signal Name Function Counter / Timer 3 Out OCTC3 Ground Ground Counter / Timer 4 In ICTC4 Ground Ground...

  • Page 56: Jd - Keyboard Connector

    External Connections JD – K EYBOARD ONNECTOR A standard IBM PC keyboard can be attached to connector JD. Table 20: Keyboard Connector Pinout 6-Pin Mini DIN PS/2 Style Signal Name Function Keyboard Data KBDATA No Connection Ground 5VCC Keyboard Clock KBCLK No Connection 46 –...

  • Page 57: Jf - Hard Disk Drive Connector

    External Connections JF – H RIVE ONNECTOR Two standard IDE drives can be connected to the VL-586-1 through this connector. Caution Cable length must be 18" or less to maintain proper signal integrity. The grounds in this connector should not be used to carry motor current. Table 21: IDE Hard Drive Connector Pinout 40-Pin Female IDC Signal...

  • Page 58: J2 - Interrupt Connector

    External Connections J2 – I NTERRUPT ONNECTOR A 4-pin header connector, J2, provides external access to two interrupt lines. Table 22: Front Plane Interrupt Connector Pinout. Signal Name Function Ground Ground FP0* Front Plane 0 Interrupt Ground Ground FP1* Front Plane 1 Interrupt FP0* —...

  • Page 59: J3 - Floppy Disk Drive Connector

    External Connections J3 – F LOPPY RIVE ONNECTOR The VL-586-1 CPU card supports a standard 34-pin PC/AT style floppy disk interface at connector J3. Note Note that Drive A and Drive B are reversed compared to a typical PC system. This was done to accommodate a single Drive A using a straight ribbon cable without a twist.

  • Page 60: L1 - Speaker Connector

    External Connections L1 – S PEAKER ONNECTOR Connector L1 is provided for connecting an 8Ω speaker to the card. Table 24: Speaker Connector Pinout. Signal Name Function Timer 2 Out Speaker drive Ground Ground 50 – Installation VL-586-1 Reference Manual...

  • Page 61: Register Descriptions

    DMA 2 Controller DMA Page COM1 Serial Port COM2 Serial Port LPT1 Parallel Port 82C735 Configuration Interrupt Controller (Master) Interrupt Controller (Slave) Counter/Timer (Channels 0 - 2) Counter/Timer (Channels 3 - 5) VersaLogic Registers VL-586-1 Reference Manual Register Descriptions – 51...

  • Page 62: Direct Memory Access - Channel 1

    Register Summary — C IRECT EMORY CCESS HANNEL Table 26: DMA 1 Controller Registers Mnemonic Address Name DMA0ADRA 0000h DMA Channel 0 Current Address DMA0CNTA 0001h DMA Channel 0 Current Word Count DMA1ADRA 0002h DMA Channel 1 Current Address DMA1CNTA 0003h DMA Channel 1 Current Word Count DMA2ADRA...

  • Page 63: Direct Memory Access - Channel 2

    Register Summary — C IRECT EMORY CCESS HANNEL Table 27: DMA 2 Controller Registers Mnemonic Address Name DMA0ADRB 00C0h DMA Channel 0 Current Address DMA0CNTB 00C2h DMA Channel 0 Current Word Count DMA1ADRB 00C4h DMA Channel 1 Current Address DMA1CNTB 00C6h DMA Channel 1 Current Word Count DMA2ADRB...

  • Page 64: Com1 Serial Port

    Register Summary COM1 S ERIAL Table 29: COM1 Serial Port Registers Mnemonic Address Name RBRA 03F8h Receiver Buffer Register A THRA 03F8h Transmit Holding Register A DLLA 03F8h Divisor Latch (LSB) A IERA 03F9h Interrupt Enable Register A DLMA 03F9h Divisor Latch (MSB) A IIRA 03FAh...

  • Page 65: Lpt1 Parallel Port

    Register Summary LPT1 P ARALLEL Table 31: LPT1 Parallel Port Registers Mnemonic Address Name LPRD 0278h Line Printer Read Data Register LPWD 0278h Line Printer Write Data Register 0279h Line Printer Status Register LPRC 027Ah Line Printer Read Control Register LPWC 027Ah Line Printer Write Control Register...

  • Page 66: Floppy Disk Drive Controller

    Register Summary LOPPY RIVE ONTROLLER Table 32: Floppy Disk Drive Controller Registers Mnemonic Address Name FDCMSR 03F4h Main Status Register FDCDR 03F5h Data Register FDCST0 03F5h Status Register 0 FDCST1 03F5h Status Register 1 FDCST2 03F5h Status Register 2 FDCST3 03F5h Status Register 3 FDCDCR...

  • Page 67: Interrupt Controller - Master

    Register Summary — M NTERRUPT ONTROLLER ASTER Table 34: Master Interrupt Controller Registers Mnemonic Address Name ICW1A 0020h Initialization Command Word 1 ICW2A 0021h Initialization Command Word 2 ICW3A 0021h Initialization Command Word 3 ICW4A 0021h Initialization Command Word 4 OCW1A 0021h Operation Command Word 1 (Interrupt Mask)

  • Page 68: Counter/Timers

    Register Summary OUNTER IMERS Table 36: Channels 0 to 2 Mnemonic Address Name T0CNT 0040h Timer 0 Count Load/Read T1CNT 0041h Timer 1 Count Load/Read T2CNT 0042h Timer 2 Count Load/Read TCW0 0043h Timer Control Word Table 37: Channels 3 to 5 Mnemonic Address Name...

  • Page 69: Special Control Register

    Register Summary PECIAL ONTROL EGISTER SCR (READ/WRITE) 00E0H Reserved Reserved Reserved WDOGEN Table 39: Special Control Register Bit Assignments Mnemonic Description Light Emitting Diode — Controls the on-board LED. LED = 0 Turns LED off. LED = 1 Turns LED on. —...

  • Page 70: Watchdog Timer Hold-Off Register

    Register Summary ATCHDOG IMER EGISTER WDHOLD (WRITE ONLY) 00E1H A watchdog timer circuit is included on the CPU card to reset the CPU if proper software execution fails or a hardware malfunction occurs. The watchdog timer is enabled/disabled by writing to bit D0 of SCR If the watchdog timer is enabled, software must periodically refresh the watchdog timer at a rate faster than the timer is set to expire (250 ms).

  • Page 71: I/Oand Memory Map Control Register

    Register Summary EMORY ONTROL EGISTER IOMMAP (WRITE ONLY) 00E2H Reserved Reserved Reserved Reserved MMAP2 MMAP1 IOMAP2 IOMAP1 Table 40: I/O and Memory Map Register Bit Assignments Mnemonic Description D7-D4 — Reserved — These bits have no function. Always read as 0. MMAP2 Memory Map Select 2 —...

  • Page 72: Map And Paging Control Register

    Register Summary AP AND AGING ONTROL EGISTER MPCR (READ/WRITE) 00E3H FPAGE Reserved RPG5 RPG4 RPG3 RPG2 RPG1 RPG0 Table 41: Map and Paging Control Register Bit Assignments Mnemonic Description FPAGE Flash Paging Enable — Enables a 64K page frame from E0000h to EFFFFh. Used to gain access to the on-board FLASH or BBSRAM.

  • Page 73: Appendix A - Schematic

    Appendix A — Schematic VL-586-1 Reference Manual Appendix A — Schematic – 63...
  • Page 74 Schematic 64 – Schematic VL-586-1 Reference Manual...
  • Page 75 Schematic VL-586-1 Reference Manual Schematic – 65...
  • Page 76 Schematic 66 – Schematic VL-586-1 Reference Manual...
  • Page 77 Schematic VL-586-1 Reference Manual Schematic – 67...
  • Page 78 Schematic 68 – Schematic VL-586-1 Reference Manual...
  • Page 79 Schematic VL-586-1 Reference Manual Schematic – 69...
  • Page 80 Schematic 70 – Schematic VL-586-1 Reference Manual...
  • Page 81 Schematic VL-586-1 Reference Manual Schematic – 71...

  • Page 82: Index

    Index Battery Card Insertion and Extraction, 40 Erasing CMOS RAM, 15 Card Orientation, 40 Preventing Damage, 8 Overview, 39 Battery Backed Static RAM. See Memory Interrupts CMOS RAM. See Memory Block Diagram, 32 Connectors. See External Connectors Configuration, 32 Counter/Timers, 3 Controllers, 3, 57 Control Registers, 58 Destinations, 32...
  • Page 83 Index Memory Map, 24 Reset, 31 Multiprocessing, 30, 34 RS-232/422/485. See Serial Ports Bus Arbitration, 30 Serial Ports, 2 Determining which type, 59 Control Registers, 54 Dual Master, 30 External Connectors (JA/JE), 42, 43 Permanent Master, 30 Interrupts, 35 Reset Signals, 31 RS-232/422/485, 28, 43 Resistor Packs, 31 Setup.

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