Related Manuals for VersaLogic VL-586-1
Summary of Contents for VersaLogic VL-586-1
- Page 1 Reference Reference Reference Reference Manual Manual Manual Manual VL-586-1 5x86 Industrial CPU Card for the STD 32 Bus...
- Page 3 VL-586-1 5x86 Industrial CPU Card for the STD 32 Bus M586-1...
- Page 5 All Rights Reserved Notice: Although every effort has been made to ensure this document is error-free, VersaLogic makes no representations or warranties with respect to this product and specifically disclaims any implied warranties of merchantability or fitness for any particular purpose.
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Page 7: Table Of Contents
Table of Contents Other References ....................... vi 1. Overview ........................1 Using This Manual ......................1 Introduction ........................1 PC/AT Compatibility..................... 1 STD/STD32 Bus Compatibility................2 PC/104-Plus Compatibility ................... 2 On-Board Memory ....................2 Hard Disk and Floppy Disk Interface..............2 Serial Ports...................... - Page 8 Table of Contents Memory Configuration ..................... 22 ROM Configuration..................... 22 DRAM Configuration..................22 CMOS RAM Configuration ................23 Battery Backed SRAM Configuration..............23 Memory Map ....................... 24 I/O Configuration ......................25 Using 8-Bit STD Bus I/O Cards ................25 Using 10-Bit STD Bus I/O Cards ................ 25 Using 16-Bit STD Bus I/O Cards ................
- Page 9 Table of Contents 5. Register Descriptions .....................51 Introduction ........................51 Register Summary ......................51 Direct Memory Access — Channel 1..............52 Direct Memory Access — Channel 2..............53 Direct Memory Access — Page Registers ............53 COM1 Serial Port ....................54 COM2 Serial Port ....................
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Page 10: Other References
Other References Other References Acer Laboratories Inc., (408) 764-0644, http://www.ali.com.tw M1489 / M1487 486 PCI Chipset Data Book Chips and Technologies, Inc., (408) 434-0600, http://www.chips.com 82C735 Super I/O Chip Data Book STD 32 Manufacturers Group, (800) 733-2111, http://www.std32.com STD 32 Bus Specification and Designer’s Guide Advanced Micro Devices (800) 222-9323, http://www.amd.com AM486DX5-133V17BHC Data Book Additional Resources,... -
Page 11: Overview
Chapter 2 – DOS Based Quick Start Describes how to quickly get your DOS based system set up and running using a VL-586-1 CPU card. Chapter 3 – Configuration Describes how to jumper the CPU card. -
Page 12: Std/Std32 Bus Compatibility
STD/STD32 B OMPATIBILITY The VL-586-1 CPU card complies with certain subsets of the STD 32 Bus specification that allow it to communicate with STD 80 compatible 8-bit and STD 32 compatible 16-bit I/O and memory cards. In addition, the card fully complies with the STD 80 Bus specification using a bus speed of 8.33 MHz. -
Page 13: Parallel Port
DMA C ONTROLLERS The VL-586-1 has two DMA controllers which provide a total of eight DMA channels (four 8-bit channels and four 16-bit channels.) DMA control signals for seven channels are available on the PC/104 Bus. The remaining 16-bit channel is accessible only by software. DMA control signals are not available on the STD Bus, PCI Bus, or via front plane connector. -
Page 14: Technical Specifications
STD 80: Full compliance, 8.33 MHz bus speed STD 32: Permanent Master, SA16, SA8 I, MB, MX STD 32: Temporary Master, SA16, SA8 I, MB, {MX} PC/104: Full compliance PC/104-Plus: Full compliance Specifications are subject to change without notice. 4 – Overview VL-586-1 Reference Manual... -
Page 15: Technical Support
Technical Support Technical Support If you have problems that this manual can’t help you solve, contact VersaLogic for technical support at (800) 824-3163 or (541) 485-8575. You can also reach VersaLogic by e-mail at info@versalogic.com. EPAIR ERVICE If your product requires service, you must obtain a Returned Material Authorization (RMA) number by calling (800) 824-3163. -
Page 17: Dos Based Quick Start
A minimum DOS based run time system requires the CPU card, a BIOS, and a boot device containing an operating system and an application program. In many cases a video card, keyboard, and monitor are added to this list, however, the VL-586-1 does not demand their presence in order to boot. -
Page 18: Installation
To prevent damage to the lithium battery, do not use black conductive foam or metal foil. Warning! The lithium battery may explode if mistreated. Do not recharge, disassemble, or dispose of in fire. Dispose of used batteries promptly. 8 – DOS Based Quick Start VL-586-1 Reference Manual... -
Page 19: Jumper Locations
Jumper Locations Jumper Locations Note Jumpers and resistor packs shown in as-shipped configuration. Figure 1. VL-586-1 CPU Card Layout VL-586-1 Reference Manual DOS Based Quick Start – 9... -
Page 20: Card Installation
Card Installation Card Installation A typical development system consists of a six-slot V32-06T Card Cage, populated with: • VL-586-1 CPU Card (with attached EPM-SVGA PC/104-Plus Video Module) • IDE Hard Disk Drive • Floppy Disk Drive A VGA compatible monitor and a PC/AT compatible keyboard are also required to complete the set of hardware necessary for development purposes. -
Page 21: Monitor Installation
Monitor Installation Monitor Installation A VGA monitor should be connected to the EPM-SVGA module as shown . Figure 2. Jumpers/Connections for an EPM-SVGA Using a VGA Monitor VL-586-1 Reference Manual DOS Based Quick Start – 11... -
Page 22: Cable Installation
Cable Installation Cable Installation To bring the header connectors on the VL-586-1 CPU card out to industry standard PC pinouts, the VersaLogic cable VL-CBL-100A is used. CMOS RAM Setup The VL-586-1 CPU card uses battery-backed, non-volatile CMOS RAM provided by the real time clock chip to store system configuration settings. -
Page 23: Cmos Setup Options
CMOS Setup Options CMOS Setup Options CMOS S ETUP SYSTEM BIOS SETUP - UTILITY VERSION 2.001.xxx (C) 1994-1996 VERSALOGIC, CORP. ALL RIGHTS RESERVED Basic CMOS Configuration Advanced Configuration Shadow Configuration Format Integrated Flash Disk Reset CMOS to last known values... -
Page 24: Reset Cmos To Factory Defaults
CMOS checksum is updated and the CPU card is rebooted. CMOS ITHOUT HANGING This option acts like a cancel function. Use it to exit Setup without changing CMOS RAM. 14 – DOS Based Quick Start VL-586-1 Reference Manual... -
Page 25: Clearing The Cmos Ram
Do not apply power to the CPU card with jumper V6[1-2] installed, doing so may damage the chipset and void the warranty. Jumper V6[1-2] is only briefly used to clear the CMOS RAM. Figure 3. CMOS RAM Jumper VL-586-1 Reference Manual DOS Based Quick Start – 15... -
Page 27: Configuration
Configuration This chapter describes how to configure the on-board options for the VL-586-1 CPU card. Configuration involves both hardware (jumper) and software (CMOS Setup) configuration. The jumpers configure the circuitry on the card for various modes of operation. The CMOS Setup configuration completes the process by establishing default operating conditions. -
Page 28: Jumper Block Locations
Hardware Jumper Summary UMPER LOCK OCATIONS Note Jumpers and resistor packs shown in as-shipped configuration. Figure 5. Jumper Block Locations 18 – Configuration VL-586-1 Reference Manual... - Page 29 Note! V8 is for factory use only. — — 25 MHz — 33 MHz V9[1-2] CPU Internal Clock Speed (AMD Only) Note! V9 is for factory use only. — — 133 MHz — 100 MHz VL-586-1 Reference Manual Configuration – 19...
- Page 30 — Connects IPC signal to STD Bus INTRQ* (P44) — Disconnects IPC from INTRQ* V17[2-3] IPC Configuration (IPC / INTRQ4* interconnect) — Connects IPC signal to STD Bus INTRQ4* (P05) — Disconnects IPC from INTRQ4* 20 – Configuration VL-586-1 Reference Manual...
- Page 31 — Dual master mode. Uses BUSAK* (P41) for bus arbitration. — Permanent or temporary master mode. V19[5-6] Multiprocessor Configuration — Dual master mode. Uses BUSRQ* (P42) for bus arbitration. — Permanent or temporary master mode. VL-586-1 Reference Manual Configuration – 21...
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Page 32: Memory Configuration
Memory Configuration Memory Configuration ROM C ONFIGURATION The VL-586-1 on-board ROM socket (U3) accepts 128Kx8 or 512Kx8, 32 pin plastic or 32 PLCC pin J-lead ceramic part(s). An extractor tool (such as VersaLogic part number VL-HDW-202) is required to remove the rectangular device without damage. -
Page 33: Cmos Ram Configuration
Table 6: CMOS RAM Jumpers Jumper Block Description Shipped V5[1-2] Battery Backed SRAM Power Note! V5 is for factory use only. Varies — Power applied to Battery Backed SRAM — Power removed from Battery Backed SRAM VL-586-1 Reference Manual Configuration – 23... -
Page 34: Memory Map
Frame (0E0000h to 0EFFFFh). See IOMMAP and MPCR registers starting on page 61 for further information. Two settings in the Advanced Configuration screen of the CMOS Setup menu control the memory region from C8000 to D7FFF and direct this area to the PC/104 or STD/STD 32 Bus. 24 – Configuration VL-586-1 Reference Manual... -
Page 35: I/O Configuration
I/O Configuration I/O Configuration In addition to on-board I/O devices, the VL-586-1 also supports STD/STD 32 Bus I/O cards and PC/104 (and PC/104-Plus) modules. The total I/O space of the CPU card is 64K. The actual I/O map of the system is defined by the fixed addresses of the on-board devices in conjunction with the addresses used by external STD Bus and PC/104 modules. -
Page 36: Using 16-Bit Std Bus I/O Cards
1000h Always enabled PC/104 M SING ODULES All PC/104 modules decode 10 address bits (A0 - A9) and will work properly with the VL-586-1 when addressed in the following I/O ranges: • − 16Fh 100h IOMAP2 Bit must = 0. See page 27. -
Page 37: I/O Map
IOMAP1 0 = PC/104 Bus 1 = STD Bus 03F0h 03FFh On Board Devices 0400h 0FFFh PC/104 Bus 1000h FBFFh STD Bus (IOEXP Signal Driven High) FC00h FFFFh STD Bus (IOEXP Signal Driven Low) VL-586-1 Reference Manual Configuration – 27... -
Page 38: Com2 Configuration
Removing V1[9-10] leaves the data circuit unterminated so that COM2 can be used as an intermediate station in an RS-485 multidrop system. When COM2 is used in multidrop operations, remove jumper V1[9-10] from all stations except both ends of the line. 28 – Configuration VL-586-1 Reference Manual... - Page 39 — RS-422 mode. Permanently enables the differential line driver. V1[9-10] RS-422/485 Transmission Line Termination — Terminates data circuit with 100 Ω resistor (RS-422, or RS-485 endpoint stations only) — Leaves data circuit unterminated (RS-485 intermediate multidrop stations only) VL-586-1 Reference Manual Configuration – 29...
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Page 40: Multiprocessor Configuration
Multiprocessor Configuration Multiprocessor Configuration The VL-586-1 CPU card supports multiple master operation for systems requiring additional processing capability or for “smart I/O” operations. In a multiple master system, one CPU must be configured as a permanent master and other CPUs are configured as temporary masters. In this scheme, a bus arbiter plugged into Slot X is used to arbitrate access to the bus. -
Page 41: Resistor Pack Configuration
SYSRESET* arriving from the permanent master via the bus. A temporary master should never respond directly to PBRESET* nor drive SYSRESET*. Dual Master — Same as temporary master mode. VL-586-1 Reference Manual Configuration – 31... -
Page 42: Interrupt Configuration
Interrupt Configuration Interrupt Configuration Seven three-position jumper blocks are used to configure the interrupt sources on the VL-586-1. Each jumper block is used to select one of two interrupt sources and route it to the interrupt controller. Wire wrap techniques can be used to route interrupt sources to the CPU’s IRQ inputs if the factory provided jumpers do not provide suitable connections. -
Page 43: Interrupt Configuration Jumpers
— Connects IPC signal to STD Bus INTRQ* (P44) — Disconnects IPC from INTRQ* V17[2-3] IPC Configuration (IPC / INTRQ4* interconnect) — Connects IPC signal to STD Bus INTRQ4* (P05) — Disconnects IPC from INTRQ4* VL-586-1 Reference Manual Configuration – 33... -
Page 44: Std Bus Interrupt Signals
INTRQ3* can be configured to drive IRQ12. INTRQ4* VBAT General purpose INTRQ4* can be jumpered to carry the Interprocessor Communications Interrupt (IPC) between multiple CPU’s by inserting jumper V17[2-3]. The IPC signal is hardwired to IRQ5. 34 – Configuration VL-586-1 Reference Manual... -
Page 45: Cpu Interrupt Request Inputs
PC/104 IRQ5 LPT 2 STD Bus IPC Interrupts or PC/104 bus. Disconnected IRQ6 Floppy Disk Hardwired From floppy disk circuit or PC/104 bus.. IRQ7 LPT1 Hardwired From printer port circuit or PC/104 bus. VL-586-1 Reference Manual Configuration – 35... - Page 46 Internal signal, not available to Coprocessor the outside world. IRQ14 Hard Disk Hardwired From PC/104 Bus and on-board Drive IDE controller. IRQ15 Unassigned Front Plane From Timer 5, Front Plane Interrupt connector, or PC/104 bus. 36 – Configuration VL-586-1 Reference Manual...
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Page 47: Interprocessor Communications Interrupt Configuration
Table 13: Non-Maskable Interrupt Jumper Jumper Block Description Shipped V18[5-6] Non-Maskable Interrupt / BUS Interconnect — Connects STD Bus NMIRQ (P46*) to CPU NMI input — CPU ignores activity on STD Bus NMIRQ (P46*) VL-586-1 Reference Manual Configuration – 37... -
Page 49: Installation
To prevent damage to the lithium battery, do not use black conductive foam or metal foil. Warning! The lithium battery may explode if mistreated. Do not recharge, disassemble, or dispose of in fire. Dispose of used batteries promptly. VL-586-1 Reference Manual Installation – 39... -
Page 50: Card Insertion And Extraction
NSTALLATION The VL-586-1 card can be used alone, as a single board computer; as the only computer in a card cage with other I/O cards; or in conjunction with several other CPUs in a multiprocessing arrangement. -
Page 51: External Connections
External Connections External Connections This chapter describes the external interfaces available on the VL-586-1 CPU card. ONNECTOR UNCTIONS Table 14: Connector Functions Connector Function High Density I/O Connector Front Plane Interrupt Connector Floppy Drive Connector Speaker Connector ONNECTOR OCATIONS Figure 8. Connector Locations VL-586-1 Reference Manual Installation –... -
Page 52: High Density 100-Pin Connector
Counter / Timer 5 Out No connection Ground Address bit 0 Address bit 2 Non-Maskable Interrupt Reg. access chip select 0 Keyboard Data Reg. access chip select 1 Ground No connection Keyboard Clock Ground 42 – Installation VL-586-1 Reference Manual... -
Page 53: Ja, Je - Serial Port Connectors
Transmit Data Negative Negative Ground Ground Ground Ground — RD2+ Receive Data TD2/RD2+ Transmit/Receive Out/In Positive Data Positive Note: In RS-485 mode, do not make connection to pin 2 [TD2+] or pin 7 [TD2–]. VL-586-1 Reference Manual Installation – 43... -
Page 54: Jb - Lpt1 Parallel Port Connector
Auto feed PERR* Printer error INIT* Reset SLIN* Select input Ground Ground — Ground Ground — Ground Ground — Ground Ground — Ground Ground — Ground Ground — Ground Ground — Ground Ground — 44 – Installation VL-586-1 Reference Manual... -
Page 55: Jc - Counter/Timer
NMI* Note: The Non-Maskable Interrupt is not available on revision 1 or revision 2 of the VL-586-1 circuit board. OCTC3 — Counter / Timer 3 Output. This TTL output signal is the primary output signal for counter / timer 3. -
Page 56: Jd - Keyboard Connector
A standard IBM PC keyboard can be attached to connector JD. Table 20: Keyboard Connector Pinout 6-Pin Mini DIN PS/2 Style Signal Name Function Keyboard Data KBDATA No Connection Ground 5VCC Keyboard Clock KBCLK No Connection 46 – Installation VL-586-1 Reference Manual... -
Page 57: Jf - Hard Disk Drive Connector
JF – H RIVE ONNECTOR Two standard IDE drives can be connected to the VL-586-1 through this connector. Caution Cable length must be 18" or less to maintain proper signal integrity. The grounds in this connector should not be used to carry motor current. -
Page 58: J2 - Interrupt Connector
If jumper V16[1-2] is inserted, a low level (or high-to-low transition) applied to the FP1* pin will request an interrupt via IRQ15. In DOS configuration, this will cause an INT 77h resulting in a dispatch through the interrupt vector at 000:01DCh. 48 – Installation VL-586-1 Reference Manual... -
Page 59: J3 - Floppy Disk Drive Connector
J3 – F LOPPY RIVE ONNECTOR The VL-586-1 CPU card supports a standard 34-pin PC/AT style floppy disk interface at connector J3. Note Note that Drive A and Drive B are reversed compared to a typical PC system. This was done to accommodate a single Drive A using a straight ribbon cable without a twist. -
Page 60: L1 - Speaker Connector
External Connections L1 – S PEAKER ONNECTOR Connector L1 is provided for connecting an 8Ω speaker to the card. Table 24: Speaker Connector Pinout. Signal Name Function Timer 2 Out Speaker drive Ground Ground 50 – Installation VL-586-1 Reference Manual... -
Page 61: Register Descriptions
The Programmer’s PC Sourcebook or The Undocumented PC listed in “Other References” on page vi. Register Summary The tables in this section list all programmable registers on the VL-586-1 CPU card. They are organized in the following groups: Table 25: Programmable Registers... -
Page 62: Direct Memory Access - Channel 1
DMA Single Bit Mask Register DMAMODEA 000Bh DMA Mode Register DMACBPA 000Ch DMA Clear Byte Pointer DMAMCA 000Dh DMA Master Clear DMACMA 000Eh DMA Clear Mask Register DMAWAMA 000Fh DMA Write All Mask Register Bits 52 – Register Descriptions VL-586-1 Reference Manual... -
Page 63: Direct Memory Access - Channel 2
0087h DMA Channel 0 Page Register DMA6PG 0089h DMA Channel 6 Page Register DMA7PG 008Ah DMA Channel 7 Page Register DMA5PG 008Bh DMA Channel 5 Page Register RAPREG 008Fh Refresh Address Page Register VL-586-1 Reference Manual Register Descriptions – 53... -
Page 64: Com1 Serial Port
Interrupt Identification Register B LCRB 02FBh Line Control Register B MCRB 02FCh Modem Control Register B LSRB 02FDh Line Status Register B MSRB 02FEh Modem Status Register B SCRB 02FFh Scratchpad Register B 54 – Register Descriptions VL-586-1 Reference Manual... -
Page 65: Lpt1 Parallel Port
LPRD 0278h Line Printer Read Data Register LPWD 0278h Line Printer Write Data Register 0279h Line Printer Status Register LPRC 027Ah Line Printer Read Control Register LPWC 027Ah Line Printer Write Control Register VL-586-1 Reference Manual Register Descriptions – 55... -
Page 66: Floppy Disk Drive Controller
01F4h Cylinder Number Register Low IDECNH 01F5h Cylinder Number Register High IDEDH 01F6h Drive/Head Register IDEST 01F7h Status Register IDECMD 01F7h Command Register IDEDIR 03F7h Digital Input Register IDEFDR 03F6h Fixed Disk Register 56 – Register Descriptions VL-586-1 Reference Manual... -
Page 67: Interrupt Controller - Master
Operation Command Word 2 (Priority & Finish Control) OCW3B 00A0h Operation Command Word 3 (Mode Control) ISRB 00A0h In-Service Register IRRB 00A0h Interrupt Request Register IPWB 00A0h Interrupt Poll Word IMRB 00A1h Interrupt Mask Register VL-586-1 Reference Manual Register Descriptions – 57... -
Page 68: Counter/Timers
TCW3 0047h Timer Control Word ISCELLANEOUS Table 38: Miscellaneous PC/AT-Style Registers Mnemonic Address Name 0061h Control/Status Port RTCIDX 0070h Real Time Clock Index and NMI Mask RTCDP 0071h Real Time Clock Data Port 58 – Register Descriptions VL-586-1 Reference Manual... -
Page 69: Special Control Register
Jumper out. PM* = 1 Jumper in. WDOGEN Watchdog Enable — Enables and disables the watchdog timer reset circuit. WDOGEN = 0 Disables the watchdog timer. WDOGEN = 1 Enables the watchdog timer. VL-586-1 Reference Manual Register Descriptions – 59... -
Page 70: Watchdog Timer Hold-Off Register
If the watchdog timer is enabled, software must periodically refresh the watchdog timer at a rate faster than the timer is set to expire (250 ms). Writing a 5Ah to WDHOLD resets the watchdog time-out period, preventing the CPU from being reset for the next 250 ms. 60 – Register Descriptions VL-586-1 Reference Manual... -
Page 71: I/Oand Memory Map Control Register
02E8h to 02EFh (COM4) = PC/104 Bus 03E8h to 03EFh (COM3) IOMAP1 = 1 02E8h to 02EFh (COM4) = STD Bus 03E8h to 03EFh (COM3) Note! See I/O map on page 27 for further information. VL-586-1 Reference Manual Register Descriptions – 61... -
Page 72: Map And Paging Control Register
RPG5-RPG0 Page Select — Selects which 64K block is mapped into the page frame. RPG5 RPG4 RPG3 RPG2 RPG1 RPG0 Memory Range 8 Pages BBSRAM 8 Pages FLASH 0 32 Pages FLASH 1 62 – Register Descriptions VL-586-1 Reference Manual... -
Page 73: Appendix A - Schematic
Appendix A — Schematic VL-586-1 Reference Manual Appendix A — Schematic – 63... - Page 74 Schematic 64 – Schematic VL-586-1 Reference Manual...
- Page 75 Schematic VL-586-1 Reference Manual Schematic – 65...
- Page 76 Schematic 66 – Schematic VL-586-1 Reference Manual...
- Page 77 Schematic VL-586-1 Reference Manual Schematic – 67...
- Page 78 Schematic 68 – Schematic VL-586-1 Reference Manual...
- Page 79 Schematic VL-586-1 Reference Manual Schematic – 69...
- Page 80 Schematic 70 – Schematic VL-586-1 Reference Manual...
- Page 81 Schematic VL-586-1 Reference Manual Schematic – 71...
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Page 82: Index
SO DIMM Socket, 22 Voltage Configuration, 22 I/O and Memory Map (IOMMAP), 61 I/O Map, 25, 27 FLASH IOEXP, 25 Extractor Tool, 22 Register Summary, 51 Overview, 2 Installation Page Frame, 24, 62 PLCC Socket, 22 VL-586-1 Reference Manual Index – 72... - Page 83 Technical Support, 5 PC/104 Bus Timers. See Counter/Timers Description, 2 Video Adapter Interrupts, 35 Installation, 10, 11 Push-button Reset, 31 Watchdog Timer Real Time Clock Enable/Disable, 59 Description, 3 Hold Off, 60 Interrupts, 35 Overview, 3 VL-586-1 Reference Manual Index – 73...
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