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K
EYPAD
Bit 6 = 1 Special synchronisation process, recognition of time leaps
In contrast to the normal synchronisation process, second leap monitoring takes place in the
special synchronisation process. Before the internal quartz clock accepts the new time in-
formation the difference between the internal clock and the new time information is calcu-
lated.
If the difference is greater than 1 second then the new time information is written to the inter-
nal clock but the hour status is set to Invalid ("–" on the display).
With this information, connected systems can reject a synchronisation. In this way a back-
wards time leap can be avoided.
For additional security the special synchronisation process should only be carried out with
two synchronisation sources.
4.3.6.3 Bit 5: Static/Dynamic Error Message
Bit 5 is used to differentiate between two different types of output. A common error message
indicates whether a major or minor alarm is present. The switch box control output (5000
system) enables a differentiation between major and minor alarm in the switch box
(see system 5000 technical manual, switch box). For error priority assignment (major, minor
or non-masked) see Chapter 4.3.9 Error Priority.
B5 = 0, Common error message
Error message out-
puts
No error
Error
B5 = 1, Switch box control
Signal outputs
Non-masked error
approx. 980/20 ms
Minor error
approx. 20/980 ms
Major error
7001GPS Satellite Clock System - V08.00
hopf Elektronik GmbH
Nottebohmstr. 41 • D-58511 Lüdenscheid • Tel.: +49 (0)2351 9386-86 • Fax: +49 (0)2351 9386-93 • Internet: http://www.hopf.com • E-Mail: info@hopf.com
This setting serves to recognise time leaps after lengthy failure of the syn-
chronisation source (> 9 hours) and subsequent synchronisation. The spe-
cial synchronisation process is provided primarily for use in the safety sys-
tem. Only here is an error message output when a time mismatch occurs. In
all other modes the synchronisation status is merely set to 'Invalid'.
TTL signal
• VG strip 7020 board pin 17b
• 9-pole SUB-D connector X1,
pin 4 (see Chapter 4.3.6.4 )
LOW level
HIGH level
TTL signal
• VG strip 7020 board pin 17b
• 9-pole SUB-D connector X1,
Pin (see Chapter 4.3.6.4 )
HIGH/ LOW level
HIGH/ LOW level
LOW level
Optocoupler
• Collector VG strip 7020
board pin 18b
• Emitter VG strip 7020
board pin 19b
Current flow
No current flow
Optocoupler
• Collector: VG strip 7020
board pin 18b
• Emitter: VG strip 7020
board pin 19b
No current flow / current
flow
No current flow / current
flow
Current
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