Comment
Signal
VCC_IO
SRST#_RDY#
FPGA_TDI
FPGA_TMS
FPGA_TCK
GND
FPGA_TDO
Not Connected
SVD_P168
SVD_P170
2.8.7
J801 – FX3 Connector
The main purpose of this connector is to access the JTAG port of the Cypress FX3 USB 3.0 controller. In
addition, this connector feeds out four GPIO pins of the FX3 that can be used if the slave FIFO interface
is not operated in 32 Bit mode. The SYSMON and VBAT signals are also accessible on this connector as
well as the FX3 reset signal that can be pulled down to reset the Cypress FX3 USB controller. All signals
on this connector are ESD protected.
Warning
The IO pins are directly connected to the Cypress FX3 USB 3.0 controller or other
peripherals. Only apply VCC_IO compliant voltages to the IO pins. Any other voltages
may damage the FX3 as well as other devices on the Mars PM3 Board.
Comment
Signal
12V
VCC_MAIN
GND
VCC_3V3
VBAT_IN
SYSMON_GPI
FX3_TRST#
FX3_TMS
FX3_TDO
FX3_TDI
FX3_TCK
23/04/2019
Connector Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Table 6: J800 – FPGA JTAG connector
Connector Pin
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
Table 7: J801 – FX3 connector
18 / 43
Signal
VCC_IO
GND
GND
GND
GND
GND
GND
GND
GND
GND
Signal
FX3_RESET_EXT#
VCC_5V
BOOT_MODE
GND
SYSMON_GPO#
FX3_GPIO0
FX3_GPIO1
FX3_GPIO2
FX3_GPIO3
GND
Comment
Comment
Version 1.09
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