Ontario Mem & Pcie I/F, Ap - Clevo W270BUQ Series Service Manual

ONTARIO MEM & PCIE I/F, AP
5 , 6 M E M _A D D R [ 1 5 : 0 ]
MEM _ ADD R0
M _AD D 0
ME M _ A D D R 1
H 19 O N T AR I O ( 2. 0)
M _AD D 1
ME M _ A D D R 2 J 17 PA R T 1 O F 5
M _AD D 2
ME M _ A D D R 3
H 18
M _AD D 3
ME M _ A D D R 4 H 17
M _AD D 4
ME M _ A D D R 5 G 17
M _AD D 5
ME M _ A D D R 6
H 15
M _AD D 6
ME M _ A D D R 7 G 18
M _AD D 7
ME M _ A D D R 8 F 19
M _AD D 8
ME M _ A D D R 9
E 19
M _AD D 9
ME M _ A D D R 1 0 T 19
M _AD D 10
ME M _ A D D R 1 1 F 17
M _AD D 11
ME M _ A D D R 1 2
E 18
M _AD D 12
ME M _ A D D R 1 3 W 17
M _AD D 13
ME M _ A D D R 1 4
E 16
M _AD D 14
ME M _ A D D R 1 5 G 15
M _AD D 15
R 18
5, 6 ME M _ B A N K 0 M _BA N K 0
T 18
M _BA N K 1
5, 6 ME M _ B A N K 1
F 16
M _BA N K 2
5, 6 ME M _ B A N K 2
5 , 6 M E M _D M[ 7 : 0 ]
D 15
ME M _ D M 0
M _D M 0
ME M _ D M 1 B 19
M _D M 1
ME M _ D M 2 D 21
M _D M 2
H 22
ME M _ D M 3
M _D M 3
ME M _ D M 4 P 23
M _D M 4
V 23
ME M _ D M 5
M _D M 5
ME M _ D M 6 A B 20
M _D M 6
ME M _ D M 7 A A 16
M _D M 7
A 16
M _D Q S _H 0
5 , 6 ME M_ D Q S _ H 0
B 16
5 , 6 ME M_ D Q S _ L 0 M _D Q S _L0
B 20
M _D Q S _H 1
5 , 6 ME M_ D Q S _ H 1
A 20
5 , 6 ME M_ D Q S _ L 1 M _D Q S _L1
E 23
M _D Q S _H 2
5 , 6 ME M_ D Q S _ H 2
E 22
M _D Q S _L2
5 , 6 ME M_ D Q S _ L 2
J 22
5 , 6 ME M_ D Q S _ H 3 M _D Q S _H 3
J 23
5 , 6 ME M_ D Q S _ L 3 M _D Q S _L3
R 22
M _D Q S _H 4
5 , 6 ME M_ D Q S _ H 4
P 22
5 , 6 ME M_ D Q S _ L 4 M _D Q S _L4
W 22
5 , 6 ME M_ D Q S _ H 5 M _D Q S _H 5
V 22
M _D Q S _L5
5 , 6 ME M_ D Q S _ L 5
A C 20
5 , 6 ME M_ D Q S _ H 6 M _D Q S _H 6
A C 21
M _D Q S _L6
5 , 6 ME M_ D Q S _ L 6
A B 16
5 , 6 ME M_ D Q S _ H 7 M _D Q S _H 7
A C 16
5 , 6 ME M_ D Q S _ L 7 M _D Q S _L7
M 17
5 M E M_ C L K _ H 0 M _C LK_ H 0
M 16
5 M E M_ C L K _ L0 M _C LK_ L0
M 19
M _C LK_ H 1
5 M E M_ C L K _ H 1
M 18
5 M E M_ C L K _ L1 M _C LK_ L1
N 18
6 M E M_ C L K _ H 2 M _C LK_ H 2
N 19
M _C LK_ L2
6 M E M_ C L K _ L2
L 18
6 M E M_ C L K _ H 3 M _C LK_ H 3
L 17
M _C LK_ L3
6 M E M_ C L K _ L3
L 23
5 , 6 M E M_ R E S E T # M _R E SE T_L
N 17
M _EV EN T_L
5 , 6 M E M_ E V E N T #
F 15
M _C K E0
5 , 6 ME M_ C K E 0
E 15
5 , 6 ME M_ C K E 1 M _C K E1
W 19
M 0_O D T 0
5 D I MM 0 _ OD T0
V 15
5 D I MM 0 _ OD T1 M 0_O D T 1
U 19
6 D I MM 1 _ OD T0 M 1_O D T 0
W 15
M 1_O D T 1
6 D I MM 1 _ OD T1
T 17
5 D I MM 0 _ C S # 0 M 0_C S_L0
W 16
M 0_C S_L1
5 D I MM 0 _ C S # 1
U 17
6 D I MM 1 _ C S # 0 M 1_C S_L0
V 16
6 D I MM 1 _ C S # 1 M 1_C S_L1
U 18
5 , 6 ME M_ R A S # M _R A S_L
V 19
M _C A S_L
5 , 6 ME M_ C A S #
V 17
M _WE _L
5 , 6 ME M_ W E #
ON T A R I O _ A P U
Res er ve 3 /1 1
ME M _ C K E 0
ME M _ C K E 1
C lose to APU
ONTARIO MEM & PCIE I/F, AP
ME M_ D A TA [ 6 3: 0 ] 5 , 6
U 1E
B 1 4 M E M_ D A T A 0
M _D AT A0
A 1 5 M E M_ D A T A 1
M _D AT A1
A 1 7
M _D AT A2 M E M_ D A T A 2
D 1 8 M E M_ D A T A 3
M _D AT A3
A 1 4
M E M_ D A T A 4
M _D AT A4
C 1 4 M E M_ D A T A 5
M _D AT A5
C 1 6 M E M_ D A T A 6
M _D AT A6
D 1 6
M E M_ D A T A 7
M _D AT A7
C 1 8 M E M_ D A T A 8
M _D AT A8
A 1 9
M _D AT A9 M E M_ D A T A 9
B 2 1 M E M_ D A T A 1 0
M _ D AT A10
D 2 0 M E M_ D A T A 1 1
M _ D AT A11
A 1 8
M E M_ D A T A 1 2
M _ D AT A12
B 1 8 M E M_ D A T A 1 3
M _ D AT A13
A 2 1
M E M_ D A T A 1 4
M _ D AT A14
C 2 0 M E M_ D A T A 1 5
M _ D AT A15
C 2 3
M E M_ D A T A 1 6
M _ D AT A16
D 2 3 M E M_ D A T A 1 7
M _ D AT A17
F 2 3 M E M_ D A T A 1 8
M _ D AT A18
F 2 2
M E M_ D A T A 1 9
M _ D AT A19
C 2 2 M E M_ D A T A 2 0
M _ D AT A20
D 2 2 M E M_ D A T A 2 1
M _ D AT A21
F 2 0
M E M_ D A T A 2 2
M _ D AT A22
F 2 1 M E M_ D A T A 2 3
M _ D AT A23
H 2 1 M E M_ D A T A 2 4
M _ D AT A24
H 2 3 M E M_ D A T A 2 5
M _ D AT A25
K 2 2
M E M_ D A T A 2 6
M _ D AT A26
K 2 1 M E M_ D A T A 2 7
M _ D AT A27
G2 3 M E M_ D A T A 2 8
M _ D AT A28
H 2 0
M E M_ D A T A 2 9
M _ D AT A29
K 2 0 M E M_ D A T A 3 0
1 V S
M _ D AT A30
K 2 3 M E M_ D A T A 3 1
M _ D AT A31
R 2 2K _1 % _ 0 4
N 2 3 M E M_ D A T A 3 2
M _ D AT A32
P 2 1
M E M_ D A T A 3 3
M _ D AT A33
T 20 M E M_ D A T A 3 4
M _ D AT A34
T 23 M E M_ D A T A 3 5
M _ D AT A35 7 C _ U M I _ P _ R X 0
M2 0
M E M_ D A T A 3 6
M _ D AT A36 7 C _ U M I _ N _ R X 0
P 2 0 M E M_ D A T A 3 7
M _ D AT A37
R 2 3 M E M_ D A T A 3 8
M _ D AT A38 7 C _ U M I _ P _ R X 1
T 22
M E M_ D A T A 3 9
M _ D AT A39
7 C _ U M I _ N _ R X 1
V 2 0 M E M_ D A T A 4 0
M _ D AT A40 7 C _ U M I _ P _ R X 2
V 2 1
M _ D AT A41 M E M_ D A T A 4 1
7 C _ U M I _ N _ R X 2
Y 2 3 M E M_ D A T A 4 2
M _ D AT A42
Y 2 2
M E M_ D A T A 4 3
M _ D AT A43 7 C _ U M I _ P _ R X 3
T 21 M E M_ D A T A 4 4
M _ D AT A44
7 C _ U M I _ N _ R X 3
U 2 3 M E M_ D A T A 4 5
M _ D AT A45
W 2 3
M E M_ D A T A 4 6
M _ D AT A46
Y 2 1 M E M_ D A T A 4 7
M _ D AT A47
Y 2 0
M _ D AT A48 M E M_ D A T A 4 8
A B 2 2 M E M_ D A T A 4 9
M _ D AT A49
A C 1 9 M E M_ D A T A 5 0
M _ D AT A50
A A 1 8
M E M_ D A T A 5 1
M _ D AT A51
A A 2 3 M E M_ D A T A 5 2
C 84 2 C 8 4 3
M _ D AT A52
A A 2 0
M E M_ D A T A 5 3
M _ D AT A53
A B 1 9 M E M_ D A T A 5 4
1 0 u _ 6 . 3V _X 5 R _0 6
M _ D AT A54
Y 1 8 M E M_ D A T A 5 5 1 0 00 p _ 5 0V _X 7 R _0 4
M _ D AT A55
A C 1 7 M E M_ D A T A 5 6
M _ D AT A56
Y 1 6 M E M_ D A T A 5 7
M _ D AT A57
A B 1 4
M E M_ D A T A 5 8 1 . 5 V
M _ D AT A58
A C 1 4 M E M_ D A T A 5 9
M _ D AT A59
A C 1 8 M E M_ D A T A 6 0
M _ D AT A60
A B 1 8
M E M_ D A T A 6 1
M _ D AT A61
A B 1 5 M E M_ D A T A 6 2
R 6 7 8
M _ D AT A62
A C 1 5
M E M_ D A T A 6 3 1K _1 % _ 0 4
M _ D AT A63
D el R 68 0 3 /7
M2 3
M _VR EF
1 . 5 V
R 6 8 1
M2 2 ME M_ Z V D D I O
R 6 3 9 . 2 _ 1% _ 0 4 1K _1 % _ 0 4
M _Z VD D I O _M EM _S
R6 co nn ect ion t o 1. 5V sh ould
be direct ly to t he plane wit ho ut a lo ng t ra ce
R 8 1 *6 8 _ 1% _ 0 4
R 8 2 *6 8 _ 1% _ 0 4
De l ? ? VGA 3 /8
U 1 A
A A 6 A B 6
P_G P P_R XP 0 P _G PP_ TXP 0
Y 6 A C 6
P_G P P_R XN 0 P _G PP_ TXN 0
O N T AR I O ( 2. 0 )
A B 4 A B 3
PA R T 2 O F 5
P_G P P_R XP 1 P _G PP_ TXP 1
A C 4 A C 3
P_G P P_R XN 1 P _G PP_ TXN 1
A A 1 Y 1
P_G P P_R XP 2 P _G PP_ TXP 2
A A 2 Y 2
P_G P P_R XN 2 P _G PP_ TXN 2
Y 4 V 3
P_G P P_R XP 3 P _G PP_ TXP 3
Y 3 V 4
P_G P P_R XN 3 P _G PP_ TXN 3
Y 1 4 A A 14
O N _ Z V D D ON _Z V S S R 1
P_Z VD D _10 P_Z VS S
A A 1 2 A B 12 C 9
P_U M I _ R XP 0 P_U M I _ TXP 0
Y 1 2 A C 1 2
C 1 0
P_U M I _ R XN 0 P_U M I _ TXN 0
A A 1 0 A C 1 1 C 1 1
P_U M I _ R XP 1 P_U M I _ TXP 1
Y 1 0 A B 11
C 1 2
P_U M I _ R XN 1 P_U M I _ TXN 1
A B 1 0 A A 8 C 1 3
P_U M I _ R XP 2 P_U M I _ TXP 2
A C 1 0 Y 8
P_U M I _ R XN 2 P_U M I _ TXN 2 C 1 4
A C 7 A B 8
C 1 5
P_U M I _ R XP 3 P_U M I _ TXP 3
A B 7 A C 8
C 1 6
P_U M I _ R XN 3 P_U M I _ TXN 3
ON T A R I O_ A P U
ROUTE A-LINK DIFF PAIR @ 85 OH M +/- 1 0%
C 8 4 4
0 . 1 u _ 10 V _ X 7 R _ 0 4
CD 3 /8
Analog Thermal Sensor
3 . 3 V
Q 15
2 1
1: 2 (4 mi ls :8m il s)
V C C O U T T H E R M_ V O L T 2 0
3
C 3 6 5 C 3 6 4
GN D
*0 . 1 u _ 10 V _ X 5 R _ 0 4 * 0 . 1 u_ 1 0 V _ X 5R _ 0 4
*G 7 11 S T 9 U
1
3
2
PLACE NEAR U1
Schematic Diagrams
Sheet 2 of 43
1 . 2 7 K _ 1 % _ 04
ONTARIO MEM &
0 . 1 u_ 1 0 V _ X 7 R _ 0 4
C _ U MI _ P _ T X 0 7
0 . 1 u_ 1 0 V _ X 7 R _ 0 4
C _ U MI _ N _T X 0 7
PCIE I/F, AP
0 . 1 u_ 1 0 V _ X 7 R _ 0 4
C _ U MI _ P _ T X 1 7
0 . 1 u_ 1 0 V _ X 7 R _ 0 4
C _ U MI _ N _T X 1 7
0 . 1 u_ 1 0 V _ X 7 R _ 0 4
C _ U MI _ P _ T X 2 7
0 . 1 u_ 1 0 V _ X 7 R _ 0 4
C _ U MI _ N _T X 2 7
0 . 1 u_ 1 0 V _ X 7 R _ 0 4
C _ U MI _ P _ T X 3 7
0 . 1 u_ 1 0 V _ X 7 R _ 0 4
C _ U MI _ N _T X 3 7
ONTARIO MEM & PCIE I/F, AP B - 3