EMC-PARTNER CDN2000-06-25 User Manual page 6

CDN2000-06-25 coupling decoupling network
Generators to carry out combination wave tests
S
Legend:
RL Charging resistor
RE1 Discharge resistor
RM Shunt
Lv Inductance of the connection
A dc source charges the capacitors within the different modules via the charging resistors. Closing the
switch S discharge the capacitors into the parallel branches RE1, RE2 and EUT. When the EUT has a high
impedance the CWG generates a voltage rise defined by the serial inductance Ls and by the parallel
resistor RE2. The half value time is determined by Cs and the both RE1 // RE2. When the EUT has a low
impedance the generated current is determined by the elements Cs, Ls, Rs and the EUT.
The current and voltage waveforms are defined in IEC 61000-4-5 as follows:
Waveshapes and tolerances
I
[A]
100%
90%
10%
8 µs
20 µs
Current into short circuit
The waveforms are verified in open circuit (voc) and short circuit (isc). No load limitation exists, because for
different load impedance (EUT) the waveforms are within the open circuit voltage waveform and the short
circuit current waveform.
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Cs Impulse capacitor
Ls Inductance of the generator
RE2 Discharge resistor
MS Measurement equipment
Rise time:
Ts=8 µs ± 20%
Half value time:
Tr = 20 µs ± 20%
Under swing:
ü < 30 %
50%
Ü<30%
Test generator CWG
U
[V]
100%
90%
1,2 µs
50 µs
Voltage at no load
EUT, e.g. Motors
Figure: 1.0.3-1
S High voltage switch
Rs Serial resistor
TM1 Divider
TM2 Divider
Rise time:
Ts=1,2 µs ± 30%
Half value time:
Tr = 50 µs ± 20%
Over swing:
ü < 5 %
50%
Figure: 1.0.1-2