Lvds_Clk; Bklt_En; Blt_Ctrl; Lvds_Ddc_Clk - Seco SBC-992-pITX User Manual

LVDS_CLK+/LVDS_CLK-: LVDS Channel #0 differential Clock.
LVDS_DDC_DAT: DisplayID DDC Data line for LVDS flat Panel detection. Bidirectional signal, electrical level +3.3V_S with a 2k2Ω pull-up resistor.
LVDS_DDC_CLK: DisplayID DDC Clock line for LVDS flat Panel detection. Output signal, electrical level +3.3V_S with a 2k2Ω pull-up resistor.
Boards configured for embedded Display Port (eDP) interface, instead, will have the following signals:
eDP0_TX0+/eDP0_TX0-: embedded DP differential data pair #0.
eDP0_TX1+/eDP0_TX1-: embedded DP differential data pair #1.
eDP0_TX2+/eDP0_TX2-: embedded DP differential data pair #2.
eDP0_TX3+/eDP0_TX3-: embedded DP differential data pair #3.
eDP0_AUX+/eDP0_AUX-: embedded DP auxiliary channel differential data pair.
eDP_HPD: embedded DP Hot Plug Detect. +3.3V_S electrical level signal with 100kΩ pull-down resistor
In both configurations, the following signals are used to manage the backlight:
BKLT_EN: +5V_S electrical level Output, 10kΩ pull-up resistor, Backlight Enable signal. It can be used to turn On/Off the backlight's lamps of connected displays.
BLT_CTRL: this signal can be used to adjust the backlight brightness in displays supporting Pulse Width Modulated (PWM) regulations (+3.3V_S electrical level).
SBC-992-pITX
SBC-992-pITX User Manual - Rev. First Edition: 1.0 - Last Edition: 2.0 - Author: S.B. - Reviewed by G.G Copyright © 2016 SECO S.r.l.
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