Dpc Sequence Description - IBM 1 Series Manual

DPC Sequence Description
Refer to Figure 2-8. DPC write and DPC read sequences are executed as
follows:
1.
'Address bus bits 0-15' and 'address bus bit 16' (and 'data bus' on
write sequences) are activated by the channel. These buses are held
valid until the fall of 'address gate return,' as seen at the processor
channelinput.
The activation of address bus bit 16 causes all I/O attachments to
compare address bus bits 8—15 (the device address) with the
attachment's assigned device address(es). An equal comparison
constitutes DPC selection of the device. Upon selection, the device
examines the commandin address bus bits 0-7 (and the data bus, for
proper parity on write sequences), and applicable device internal
conditions necessary for determining command acceptance and I/O
instruction condition code reporting. No specific device action or state
change must occur as a result of the selection and examination of
conditions relative to the commanditself until: (1) 'address gate' is
recognized by the selected device for write sequences, or (2) 'data
strobe' is recognized by the selected device for read sequences. For
write sequences, the device should not change state until 'data strobe'
is recognized, except during execution of a Device Reset command. If
an I/O device has an interrupt request active on the interface and
executes a Device Reset or Prepare command, the device, as
appropriate, drops its request or alters its requested level prior to the
deactivation of 'data strobe,' as seen at the device interface.
'Address gate' is deskewed and activated on the channel. The deskew
time, CT1, between the last valid signal of 'address bus' (and 'data
bus' on write sequences) and the activation of 'address gate,' measured
at the device interface, is 200 nanoseconds, minimum. Upon
recognition of the 'address gate' by the selected device, the device
activates the 'condition code in bus' (and the 'data bus' on read
sequences) and then activates 'address gate return.'
The 'condition code in bus' (and 'data bus' on read sequences) must
be activated prior to 'address gate return,' as seen at the device
interface. These buses must be held valid and must not change in value
until the deactivation of 'address gate' and 'data strobe' at the device
interface. |
The permissible delay, T2, from 'address gate' to 'address gate return,'
as seen at the device interface, is 3 microseconds, maximum. 'Address
gate return' is timed out by the channel. If 'address gate return' does
not become active at the processor channel input within the time-out
period, condition code 0 (device not attached) is returned by the
channel to the I/O instruction, and the sequence is terminated as
follows: 'address gate' and 'address bus' (and 'data bus' on write
sequences) are deactivated. 'Data strobe' is not activated. 'Address
gate' is deactivated prior to the deactivation of 'address bus,' as seen
at the device interface.
The permissible delay, T2, allows device attachments further time to
resolve conditions for command acceptanceorto initiate interlocked
activation with further outbound logic. However, unless such functions
are necessary, 'address gate return' should be activated as soon as
possible for performance reasons.
Processor I/O Channel 2-19