IBM 1 Series Manual page 27

2-16 GA34-0033
The service and poll groups operate concurrently and asynchronously to
each other. This characteristic is a major operational and design
consideration. However, some of the sequences occurring on the I/O
channel are interdependent. Figure 2-7 is a block diagram illustrating the
architectural interdependencies of the major channel sequences from the
viewpoint of a group of devices in normal operation. This diagram does
not attempt to show contention resolution in the channel or provide a
system level description. The IPL and reset sequences are of a special
nature. IPL sequences use the poll and service groups in combination and
involve operations with only one specific device and with no other device
active. Resets are entirely asynchronous and affect operations on both
groups.
The inputs on the left side of the diagram are:
1. A processor interrupt poll request and a cycle-steal request to the poll
group. The processor generates a request for an interrupt poll only
after the priority interrupt algorithm is satisfied and the processor can
accept the interrupt. The cycle-steal request is generated by I/O
devices on the channelitself.
2. A processor DPC request to the service group, which is done inline
with the execution of an Operate I/O instruction.
Although the poll group and service group resources can be active
simultaneously, each group can have only one of its possible transactions
active at a time. Therefore, the inputs (requests) to each group must be
mutually exclusive at the instant in time the group becomesfree to gate
another transaction. If the sources of the inputs are running
asynchronously, then contention among the requests must be resolved.
Although input relationships and contention resolutions are not shown in
the diagram, the following can be assumed:
e The processor interrupt poll request and the processor DPC requests
are mutually exclusive. This occurs because the processor cannot
perform priority interrupt acceptance and execute an Operate I/O
instruction at the sametime.
¢« Contention is resolved between processor interrupt poll and cycle-steal
requests at the input to the poll group at the time the poll group
becomesfree to gate another transaction.
¢« Contention is resolved between processor DPC and poll group requests
at the input to the service group at the time the service group becomes
free to gate another transaction block.