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PEX 8311RDK
User Manuals: PLX Technology PEX 8311RDK development
Manuals and User Guides for PLX Technology PEX 8311RDK development. We have
1
PLX Technology PEX 8311RDK development manual available for free PDF download: Hardware Reference Manual
PLX Technology PEX 8311RDK Hardware Reference Manual (66 pages)
Brand:
PLX Technology
| Category:
Microcontrollers
| Size: 1 MB
Table of Contents
Table of Contents
5
1 General Information
9
Figure 1-1. PEX 8311RDK - Component Side View
9
PEX 8311 Features
10
PEX 8311RDK Features
10
2 PEX 8311RDK System Architecture
11
3 PEX 8311RDK Hardware Architecture
12
PEX 8311 PCI Express Bridge Device
12
Serial EEPROM
12
Figure 3-1. PEX 8311RDK Hardware Architecture
12
Microwire Serial EEPROM
13
Microwire Serial EEPROM Contents
14
Table 3-1. Long Serial EEPROM Load Registers
14
Spi Eeprom
13
Local and PCI Express Hardware Elements
15
Table 3-2. Extra Long Serial EEPROM Load Registers
15
Internal Clock
16
Local Clock
16
Synchronous Burst SRAM
16
Xilinx CPLD
16
PLX Option Module Connector
17
Hardware Memory Map
18
PCI Express Interface
18
Refclk
18
Perst
18
Table 3-3. PEX 8311RDK Processor/Local Bus Memory Map
18
Reset Circuitry
19
LED Indicators
19
PEX 8311RDK Power
19
PEX 8311 Bridge Device Power
19
Table 3-4. PEX 8311RDK LED Indicators
19
PEX 8311 Power Jumpers and Resistor Options
20
Table 3-5. PEX 8311RDK Power Supply Currents
20
Table 3-6. PEX 8311RDK Power Jumper and Resistor Options
20
Power Management Signaling
21
Wakeup
21
Endpoint/Root Complex Operation
21
4 Mechanical Architecture
23
Figure 4-1. PEX 8311RDK Component Placement
23
Monitoring Points, Test Headers, Indicators, Control, and DIP Switch Summary
24
Headers
24
JTAG Headers
24
Monitoring Points
24
Test Headers
24
Controls
25
Indicators
25
PEX 8311RDK Layout Information
25
Power Decoupling
25
Table 4-1. PEX 8311RDK Default Jumper Settings
25
Trace Routing Design Rules
25
Figure 4-2. PEX 8311RDK Decoupling Capacitor Footprints
26
Figure 4-3. PEX 8311RDK Stackup
26
PCB Stackup
26
Midbus LAI Footprints
27
Prototyping Area
27
Surface Mount Footprints
27
Table 4-2. Layer Thickness
27
Table 4-3. Six (6) Surface Mount Footprints
27
Uncommitted FPGA Connections
28
Uncommitted FPGA Footprint
28
Uncommitted FPGA to PEX 8311 Local Bus
28
Table 4-4. Uncommitted FPGA Resistor Configuration
29
Programming the FPGA through the JTAG Interface
32
Programming the Uncommitted FPGA
32
Table 4-5. Altera Uncommitted FPGA JTAG Interconnections
33
Table 4-6. Xilinx Uncommitted FPGA JTAG Interconnections
34
4.4.2.3.2 Programming the FPGA through the GPIO
35
Table 4-7. Programming the Altera Uncommitted FPGA through the GPIO
35
Programming the Uncommitted FPGA from the Configuration PROM
36
Table 4-8. Programming the Xilinx Uncommitted FPGA through the GPIO
36
Table 4-9. Platform Flash to Xilinx Interconnect
37
Uncommitted FPGA Power Supplies
37
Increasing the Number of Unused Uncommitted FPGA I/O
38
Uncommitted FPGA Pull-Ups/Downs
38
5 RDK Mode Configuration
39
Table 5-1. RDK Board Mode Configuration
39
6 Examples of Testing the Onboard 32Kx32 SBSRAM with Plxmon
41
7 CPLD Verilog Code
43
Verilog Code
43
8 References
47
9 Bill of Materials / Schematics
49
Table 9-1. PEX 8311RDK Bill of Materials
49
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