Infineon XC888CLM Microcontroller 8-Bit Manuals

Manuals and User Guides for Infineon XC888CLM Microcontroller 8-Bit. We have 1 Infineon XC888CLM Microcontroller 8-Bit manual available for free PDF download: User Manual

Infineon XC888CLM User Manual

Infineon XC888CLM User Manual (663 pages)

8-Bit Single Chip Microcontroller

Brand: Infineon | Category: Microcontrollers | Size: 5.98 MB

Table of Contents

Table of Contents
5
1 Introduction

15
- Feature Summary
  18
- Pin Configuration
  20
- Pin Definitions and Functions
  22
- Chip Identification Number
  31
- Text Conventions
  32
- Reserved, Undefined and Unimplemented Terminology
  33
- Acronyms
  33
2 Processor Architecture

35
- Functional Description
  35
- CPU Register Description
  37
- Stack Pointer (SP)
  37
- Data Pointer (DPTR)
  37
- Accumulator (ACC)
  37
- B Register
  37
- Program Status Word
  38
- Extended Operation (EO)
  39
- Power Control (PCON)
  40
- Instruction Timing
  40
3 Memory Organization

48
- Compatibility between Flash and ROM Devices
  50
- Program Memory
  51
- Data Memory
  51
- Internal Data Memory
  51
- External Data Memory
  52
- Memory Protection Strategy
  53
- Flash Memory Protection
  53
- Miscellaneous Control Register
  56
- Special Function Registers
  57
- Address Extension by Mapping
  57
- System Control Register 0
  59
- Address Extension by Paging
  60
- Page Register
  62
- Bit-Addressing
  63
- System Control Registers
  64
- Bit Protection Scheme
  66
- XC886/888 Register Overview
  68
- CPU Registers
  68
- MDU Registers
  69
- CORDIC Registers
  70
- System Control Registers
  71
- WDT Registers
  73
- Port Registers
  74
- ADC Registers
  76
- Timer 2 Registers
  80
- Timer 21 Registers
  80
- CCU6 Registers
  81
- UART1 Registers
  85
- SSC Registers
  86
- Multican Registers
  86
- OCDS Registers
  87
- Boot ROM Operating Mode
  88
- User Mode
  89
- Bootstrap Loader Mode
  89
- OCDS Mode
  90
- User JTAG Mode
  90
4 Flash Memory

91
- Flash Memory Map
  92
- Flash Bank Sectorization
  93
- Parallel Read Access of P-Flash
  95
- Operating Modes
  101
- Error Detection and Correction
  102
- Flash Error Address Register
  103
- In-System Programming
  104
- In-Application Programming
  105
- Flash Programming
  106
- Flash Erasing
  107
- Aborting Flash Erase
  108
- Flash Bank Read Status
  110
- P-Flash Parallel Read Enable/Disable
  110
- Get Chip Information
  111
5 Interrupt System

112
- Interrupt Structure
  119
- Interrupt Structure 1
  119
- Interrupt Structure 2
  120
- System Control Register 0
  121
- Interrupt Source and Vector
  122
- Interrupt Priority
  124
- Interrupt Handling
  125
- Interrupt Response Time
  126
- Interrupt Registers
  128
- Interrupt Node Enable Registers
  128
- External Interrupt Control Registers
  132
- Interrupt Flag Registers
  136
- Interrupt Priority Registers
  143
- Interrupt Flag Overview
  146
6 Parallel Ports

148
- General Port Operation
  149
- General Register Description
  152
- Data Register
  153
- Direction Register
  154
- Open Drain Control Register
  155
- Pull-Up/Pull-Down Device Register
  155
- Alternate Input and Output Functions
  157
- Register Map
  158
- Port 0
  160
- Functions
  160
- Register Description
  164
- Port 1
  167
- Functions
  167
- Port 2
  174
- Functions
  174
- Register Description
  177
- Port 3
  179
- Functions
  179
- Register Description
  183
- Port 4
  186
- Functions
  186
- Port 5
  186
- Register Description
  190
7 Power Supply, Reset and Clock Management

200
- Power Supply System with Embedded Voltage Regulator
  200
- Reset Control
  202
- Types of Resets
  202
- Power-On Reset
  202
- Hardware Reset
  204
- Watchdog Timer Reset
  204
- Power-Down Wake-Up Reset
  205
- Brownout Reset
  205
- Module Reset Behavior
  206
- Booting Scheme
  207
- Register Description
  208
- Clock System
  210
- Clock Generation Unit
  210
- Functional Description
  211
- Clock Source Control
  212
- Clock Management
  214
- Register Description
  216
8 Power Saving Modes

222
- Functional Description
  223
- Idle Mode
  223
- Slow-Down Mode
  223
- Power-Down Mode
  224
- Peripheral Clock Management
  226
- Register Description
  226
9 Watchdog Timer

232
- Functional Description
  233
- Module Suspend Control
  235
- Register Map
  236
- Register Description
  236
10 Multiplication/Division Unit

240
- Functional Description
  241
- Division Operation
  242
- Normalize
  242
- Shift
  242
- Busy Flag
  243
- Error Detection
  243
- Interrupt Generation
  243
- Low Power Mode
  244
- Register Map
  245
- Register Description
  246
- Operand and Result Registers
  248
- Control Register
  250
- Status Register
  252
11 CORDIC Coprocessor

253
- Features
  254
- Functional Description
  255
- Operation of the CORDIC Coprocessor
  255
- Interrupt
  256
- Normalized Result Data
  256
- CORDIC Coprocessor Operating Modes
  257
- Domains of Convergence
  259
- Overflow Considerations
  260
- CORDIC Coprocessor Data Format
  260
- Accuracy of CORDIC Coprocessor
  261
- Performance of CORDIC Coprocessor
  263
- The CORDIC Coprocessor Kernel
  264
- Arctangent and Hyperbolic Arctangent Look-Up Tables
  264
- Linear Function Emulated Look-Up Table
  265
- Low Power Mode
  266
- Register Map
  267
- Register Description
  268
- Control Register
  268
- Status and Data Control Register
  270
- Data Registers
  271
12 Serial Interfaces

273
- Uart
  274
- UART Modes
  274
- Mode 0, 8-Bit Shift Register, Fixed Baud Rate
  274
- Mode 1, 8-Bit UART, Variable Baud Rate
  275
- Mode 2, 9-Bit UART, Fixed Baud Rate
  277
- Mode 3, 9-Bit UART, Variable Baud Rate
  277
- Multiprocessor Communication
  279
- UART Register Description
  280
- Baud Rate Generation
  282
- Fixed Clock
  282
- Dedicated Baud-Rate Generator
  283
- Timer 1
  292
- Port Control
  295
- Low Power Mode
  296
- Register Map
  297
- Lin
  298
- LIN Protocol
  298
- LIN Header Transmission
  300
- Automatic Synchronization to the Host
  300
- Baud Rate Detection of LIN
  301
- High-Speed Synchronous Serial Interface
  303
- General Operation
  304
- Operating Mode Selection
  304
- Full-Duplex Operation
  305
- Half-Duplex Operation
  308
- Continuous Transfers
  309
- Port Control
  310
- Baud Rate Generation
  311
- Error Detection Mechanisms
  313
- Interrupts
  315
- Low Power Mode
  316
- Register Map
  316
- Register Description
  317
- Port Input Select Register
  317
- Configuration Register
  318
- Baud Rate Timer Reload Register
  322
- Transmit and Receive Buffer Register
  323
13 Timers

325
- Timer 0 and Timer 1
  326
- Basic Timer Operations
  326
- Mode 1
  329
- Mode 3
  331
- Port Control
  332
- Register Map
  333
- Register Description
  334
- Timer 2 and Timer 21
  338
- Basic Timer Operations
  338
- Auto-Reload Mode
  338
- Up/Down Count Disabled
  338
- Up/Down Count Enabled
  339
- Capture Mode
  342
- Count Clock
  343
- External Interrupt Function
  344
- Port Control
  344
- Low Power Mode
  345
- Module Suspend Control
  346
- Register Map
  347
- Register Description
  348
14 Capture/Compare Unit 6

353
- Functional Description
  355
- Timer T12
  355
- Timer Configuration
  356
- Counting Rules
  356
- Switching Rules
  357
- Compare Mode of T12
  358
- Duty Cycle of 0% and 100
  360
- Dead-Time Generation
  360
- Capture Mode
  361
- Single-Shot Mode
  362
- Hysteresis-Like Control Mode
  362
- Timer T13
  364
- Timer Configuration
  364
- Compare Mode
  365
- Single-Shot Mode
  365
- Synchronization of T13 to T12
  365
- Modulation Control
  367
- Trap Handling
  369
- Multi-Channel Mode
  371
- Hall Sensor Mode
  373
- Sampling of the Hall Pattern
  373
- Brushless-DC Control
  374
- Interrupt Generation
  377
- Low Power Mode
  378
- Module Suspend Control
  379
- Port Connection
  380
- Register Map
  384
- Register Description
  387
- System Registers
  389
- Timer 12 - Related Registers
  392
- Timer 13 - Related Registers
  403
- Capture/Compare Control Registers
  407
- Global Modulation Control Registers
  419
- Multi-Channel Modulation Control Registers
  425
- Interrupt Control Registers
  431
15 Controller Area Network (Multican) Controller

445
- Multican Kernel Functional Description
  448
- Module Structure
  448
- Clock Control
  451
- CAN Node Control
  452
- Bit Timing Unit
  452
- Bitstream Processor
  453
- Error Handling Unit
  454
- CAN Frame Counter
  455
- CAN Node Interrupts
  455
- Message Object List Structure
  457
- Basics
  457
- List of Unallocated Elements
  458
- Connection to the CAN Nodes
  458
- List Command Panel
  459
- CAN Node Analysis Features
  462
- Analyze Mode
  462
- Loop-Back Mode
  462
- Bit Timing Analysis
  463
- Message Acceptance Filtering
  465
- Receive Acceptance Filtering
  465
- Transmit Acceptance Filtering
  466
- Message Postprocessing
  467
- Message Interrupts
  467
- Pending Messages
  469
- Message Object Data Handling
  471
- Frame Reception
  471
- Frame Transmission
  474
- Message Object Functionality
  477
- Standard Message Object
  477
- Single Data Transfer Mode
  477
- Single Transmit Trial
  477
- Message Object FIFO Structure
  478
- Receive FIFO
  480
- Transmit FIFO
  481
- Gateway Mode
  482
- Foreign Remote Requests
  484
- Access Mediator
  485
- Port Control
  487
- Low Power Mode
  488
- Registers Description
  489
- Global Module Registers
  492
- CAN Node Registers
  503
- Message Object Registers
  520
- Multican Access Mediator Register
  541
16 Analog-To-Digital Converter

545
- Structure Overview
  546
- Clocking Scheme
  547
- Conversion Timing
  548
- Low Power Mode
  551
- Functional Description
  552
- Request Source Arbiter
  553
- Conversion Start Modes
  554
- Channel Control
  554
- Sequential Request Source
  555
- Overview
  555
- Request Source Control
  557
- Parallel Request Source
  558
- Overview
  558
- Request Source Control
  559
- External Trigger
  560
- Software Control
  560
- Autoscan
  560
- Wait-For-Read Mode
  561
- Result Generation
  561
- Overview
  561
- Limit Checking
  563
- Data Reduction Filter
  564
- Result Register View
  565
- Interrupts
  567
- Event Interrupts
  568
- Channel Interrupts
  569
- External Trigger Inputs
  571
- ADC Module Initialization Sequence
  572
- Register Map
  574
- Register Description
  577
- General Function Registers
  577
- Priority and Arbitration Register
  580
- External Trigger Control Register
  582
- Channel Control Registers
  583
- Input Class Register
  584
- Sequential Source Registers
  585
- Parallel Source Registers
  593
- Result Registers
  597
- Interrupt Registers
  603
17 On-Chip Debug Support

608
- Features
  608
- Functional Description
  609
- Debugging
  610
- Debug Events
  610
- Hardware Breakpoints
  611
- Software Breakpoints
  612
- External Breaks
  613
- NMI-Mode Priority over Debug-Mode
  613
- Debug Actions
  613
- Call the Monitor Program
  613
- Activate the MBC Pin
  614
- Debug Suspend Control
  614
- Register Description
  616
- Monitor Work Register 2
  616
- Input Select Registers
  618
- Jtag ID
  619
18 Bootstrap Loader

620
- UART and LIN BSL Modes
  621
- Communication Protocol
  622
- UART Transfer Block Structure
  622
- LIN Transfer Block Structure
  623
- Response Code to the Host
  625
- Bootstrap Loader Via UART
  627
- Communication Structure
  628
- The Selection of Modes
  629
- The Activation of Modes 1, 3 and F
  631
- The Activation of Mode 6
  631
- The Activation of Mode a
  634
- Bootstrap Loader Via LIN
  635
- Communication Structure
  636
- The Selection of Modes
  638
- The Activation of Modes 0, 2 and 8
  638
- The Activation of Modes 1, 3 and 9
  640
- The Activation of Mode 4
  640
- The Activation of Mode 6
  641
- The Activation of Mode a
  643
- LIN Response Protocol to the Host
  643
- Fast LIN BSL
  644
- After-Reset Conditions
  644
- User Defined Parameter for LIN BSL
  646
- Multican BSL Mode
  648
- Communication Protocol
  648
- CAN Message Object Definition
  649
- User Defined Parameter for Multican BSL
  651
19 Index

652
- Keyword Index
  652
- Register Index
  659

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