PLL CIRCUIT BLOCK DIAGRAM
MAIN LOOP
r-------------------------,
I
I
012-014
LOOP
FILTER
IC13
IC14
DIVIDER
1/4
VC01-VC04
0
VC01
015
VC02
017
VC03
019
VC04
021
fv:
70.9515-
100.4515 MHz
AMP
023
fv
fv-fLO:
8.5015-37.88951 MHz
BUFFER
026
LPF
AMP
027
L_ -
2.:-~~H!.,_
- - - - - - - - - - - - - - - - __
.J
r-------------------1
VC05
I
LO AMP
024
DIVIDER
1/2
DDS
LOOP
FILTER
I
fLo: 62.05-
1
62.56199 MHz
DATA
I
I
I
0.61-1.12199 MHz
I
BUFFER
+
IC17
I
I
a~
I
L - - - - - - - - - - - - - - - - - ___
J
BUFFER
034
REFERENCE
OSCILLATOR
033
MULTIPLIER
x2
036
SUB LOOP
Fig. 6
2nd LO
........ ....---• 61.44 MHz
4·4 LOGIC CIRCUITS
BAND
FREQUENCY (MHz)
BPF
VOLTAGE
4-4·1 BAND SELECTION DATA (PLL UNIT)
To select the correct bandpass filter, the low-pass filter and
VCOs on the MAIN and PLL UNITS, the CPU outputs the
following data.
R29-R40 and D29-D35 convert the "B0"-"87" signals
into a band voltage (O- 7 .5 V) for external equipment.
0.5-1.599
1.6-1.999
2.0-3.999
4.0-7.999
8.0-10.999
11.0-14.999
15.0-21.999
22.0-30.0
BO
7.5
v
81
82
5.9V
83
5.0V
B4
O.OV
85
4.1
v
86
3.2
v
87
2.2
v
1st LO to
MAIN UNIT
LPF
L1
L2
L3
L4
LS
L6
vco
VC01
VC02
VC03
VC04
Need help?
Do you have a question about the IC-725 and is the answer not in the manual?
Questions and answers