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CS-8 Series DTG Rev1.3, July 2020
The attack phase is following now a hold phase, before the decay phase starts.
But in case of returning the active Env-Gate input from +5 V to 0 V it is usually
explicit desired to finish the hold phase, immediately and return to the release
phase. This is provided by the internal and inverse connection between jack 8
(Env-Gate) and jack 7 (Gate-Reset). For other follies this unique pre-patch is
easily to untie.
8.7 Output VCA
The whole stuff, finally, is well-rounded by a VCA. This includes the CV input
control jack 23 and its output jack 24. Jack 23 is internally tied up to -5 V,
hence the output jack 24 provides normally the inverse envelope output (final
attack value of -5 V). The scale of jack 23 is 1 V/V. This refers to the final attack
value, means ±X V at jack 23 are leading to a final attack value of ±X V. The
control range reaches from -5 V to +10 V (double output voltage referring to
the regular output (jack 25)). However, the output voltage cannot exceed
+10 V, means in case of a Sustain value beyond the final attack value this is to
take into account. Otherwise the envelope output curve will be limited, that's
all.
8.8 Waveform shaping
By feed-back the envelope output to the time CV control jacks (9), (14) and
(22) a very markedly change of the envelope curve is possible. This is shown in
the Fig. 9 and Fig. 10. This feed-back will also affect the total phase time, which
is correctable by counteracting either via the time controller (10), (15), (21) or
by further adding correction voltages at the CV control jacks (9), (14) and (22).
For the decay and release phases it could become some tricky, because the
end state or the initial state, resp. is variable for these two phases. Hence, this
state influences the grade of curve bending and the time correction.
Nevertheless, very good results can achieved with this technique.
-21-
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