The Gate/Delay Section - Schippmann CS-8 Series Owner's Manual

Hint 2: A positive voltage at every of the overall 8 CV-control jacks with a scale
of 1 V/decade has an accelerating effect, means that the times of the phases
will be reduced by a factor of 10 with every applied volt.
Gt/Del
+5 V
+5 V
Gate mode (+5 V) /
CCW
Delay mode (0 V)
G-Time
Time
positve
voltages
-> shorter
1 V/
Dec.
Gate Input
Gate
+5 V
CCW
1 V/
Dec.
Attack
Env.
Env-
Gate
Gate
Input
Env.
Env-
Reset
Reset
Input
Hold Input
Hold
CV-VCA
-5 V

8.2 The Gate/Delay section

This section includes the panel elements 1-7 (26-32). The jacks 1, 2, 5 and 7 are
digital and receives or sending 0 V/+5 V. Jack 1 is the Gate input and jack 2
Gate-Reset Input
DTG's Gate
Delay phase (red) /
active Gate (green)
Gate Out
+5 V
2 col.
LED
CCW
1 V/
Dec.
Decay
Time Time
Env output (attack)
positve pos. (grn)/ neg. (red) positve
voltages voltages
-> faster -> faster
Envelope curve
-
+
Σ
VCA
Env Out
Fig. 3 Structure of the DTG (one of two)
CS-8 Series DTG Rev1.3, July 2020
Gt-Res
Inv
2 colour
LED
Gate O
+5 V
2 col. Decay active
5 V in leads to 10 V out
out
LED
CW
-5 V
Sustain
+5 V
-5 V
Env output (decay)
pos. (grn)/ neg. (red)
DTG's Env
bipolar VCA Out
-15-
+5 V
factor 2
CCW
1 V/
to
Dec.
Release
Sustain Env output (release)
pos. (grn)/ neg. (red)
level
2 col.
LED
Time
positve
voltages
-> faster