Ipmc Port Mapping; Table 3-9 Ipmc Port Mapping - GE NETernity CP921RC–30X Hardware Reference Manual

3.2.2 IPMC Port Mapping

The IPMC implements the IPMI functionality. The IPMC firmware is stored in
EEPROM. Table 3‐9 describes the port mapping for the IPMC.

Table 3-9 IPMC Port Mapping

Port
P0.0
P0.1
P0.2
P0.3
P0.4
P0.5
P0.6
P0.7
P1.0
P1.1
P1.2
P1.3
P1.4
P1.5
P1.6
P1.7
P2.0
P2.1
P2.2
P2.3
P2.4
P2.5
P2.6
P2.7
P3.0
46 NETernity CP921RC-30X Hardware Reference Manual
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Signal Description
SPI_CLK SPI clock.
C8051_MISO SPI Data (Master In — Slave Out).
C8051_MOSI SPI Data (Master Out — Slave In).
IPMB_SDA I2C add for IPMB.
IPMB_SCL I2C clock for IPMB.
UART_TX UART Transmit.
UART_RX UART Receive.
*CPCI_BDSEL CPCI board insertion, where:
0 = Board inserted.
1 = Board not inserted.
*C8051_EEPROM_CS EEPROM Chip Select, where:
0 = Program EEPROM selected.
1 = EEPROM is not selected.
TEMP_SEN1_CS Temperature Sensor #1 Chip Select, where:
0 = Sensor #1 selected.
1 = Sensor #1 not selected.
*TEMP_SEN2_CS Temperature Sensor #2 Chip Select, where:
0 = Sensor #2 selected.
1 = Sensor #2 not selected.
GA0_B CPCI GA (Geographical Address) bit 0.
GA1_B CPCI GA bit 1.
GA2_B CPCI GA bit 2.
GA3_B CPCI GA bit 3.
GA4_B CPCI GA bit 4.
*IPMI_RST_OUT IPMI reset to the rest of the board (except IPMI), where:
0 = Reset the board.
1 = Normal operation.
*BLUE_CNTL Hot Swap control, where:
0 = Okay to power down the unit.
1 = Power down not allowed.
BRD_SEL3D Signal indication from the Latch Handle Switch, where:
0 = Latch is activated.
1 = Latch is open.
*FORCEOFF Switch control, where:
0 = Turn off switch (except IPMI).
1 = Normal operations.
*IPMI_INT IPMI Interrupt, where:
0 = IPMI interrupt asserted.
1 = No interrupt.
SDA_2 Optional I2C clock bus for CPCI SMB (IPMB1).
I2C bit banging operation required.
SCL_2 Optional I2C clock bus for CPCI SMB (IPMB1).
I2C bit banging operation required.
GPIO_A GPIO signal routed to the CPLD on the CP921RC-30X
GPIO_B GPIO signal routed to the CPLD on the CP921RC-30X.