Texas Instruments eInfochips TMDXEVM6657L Technical Reference Manual
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Texas Instruments eInfochips TMDXEVM6657L Technical Reference Manual

Texas Instruments eInfochips TMDXEVM6657L Technical Reference Manual

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Technical Reference Manual
TMDXEVM6657L
TMDXEVM6657LE
SPRUHG7 - Revised August 2012
TMDXEVM6657L / TMDXEVM6657LE
Technical Reference Manual
Version 1.1
Literature Number: SPRUHG7
Revised August 2012
Document Copyright
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C6657 Lite EVM Technical Reference Manual
All Rights Reserved. Reproduction, adaptation, or
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Summary of Contents for Texas Instruments eInfochips TMDXEVM6657L

  • Page 1 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 TMDXEVM6657L / TMDXEVM6657LE Technical Reference Manual Version 1.1 Literature Number: SPRUHG7 Revised August 2012 Document Copyright Publication Title C6657 Lite EVM Technical Reference Manual All Rights Reserved. Reproduction, adaptation, or translation without prior...
  • Page 2 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 EVALUATION BOARD/KIT/MODULE (EVM) WARNINGS, RESTRICTIONS AND DISCLAIMER Not for Diagnostic Use: For Feasibility Evaluation Only in Laboratory/Development Environments The EVM may not be used for diagnostic purposes. This EVM is intended solely for evaluation and development purposes. It is not intended for use and may not be used as all or part of an end equipment product.
  • Page 3 Preface About this Document This document is a Technical Reference Manual for the TMS320C6657 Evaluation Module (C6657 Lite EVM) designed and developed by eInfochips Limited for Texas Instruments, Inc. Notational Conventions This document uses the following conventions: Program listings, program examples, and interactive displays are shown in a mono-spaced font.
  • Page 4 Trademarks The Texas Instruments logo and Texas Instruments are registered trademarks of Texas Instruments. Trademarks of Texas Instruments include: TI, XDS, Code Composer, Code Composer Studio, Probe Point, Code Explorer, DSP/BIOS, RTDX, Online DSP Lab, TMS320, TMS320C54x, TMS320C55x, TMS320C62x, TMS320C64x, TMS320C67x, TMS320C5000, and TMS320C6000.
  • Page 5 PCI Industrial Computer Manufacturers Group Reserved for Future Use SDRAM Synchronous Dynamic Random Access Memory SERDES Serializer-Deserializer SGMII Serial Gigabit Media Independent Interface SRIO Serial RapidIO UART Universal Asynchronous Receiver/Transmitter Universal Serial Bus XDS560v2 Texas Instruments’ System Trace Emulator Page 5 / 90...

  • Page 6: Table Of Contents

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Table of Contents OVERVIEW ................................11 KEY FEATURES .............................. 11 FUNCTIONAL OVERVIEW..........................12 BASIC OPERATION ............................14 BOOT MODE AND BOOT CONFIGURATION SWITCH SETTING............. 15 POWER SUPPLY ............................. 16 INTRODUCTION TO THE C6657 LITE EVM BOARD ..................17 MEMORY MAP ..............................
  • Page 7 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 COM1, UART 3-PIN CONNECTOR ........................ 41 3.2.3 COM_SEL1, UART ROUTE SELECT CONNECTOR ................... 41 3.2.4 3.2.5 DC_IN1, DC POWER INPUT JACK CONNECTOR ..................42 EMU1, TI 60 PIN DSP JTAG CONNECTOR....................42 3.2.6 3.2.7 HYPERLINK1, HYPERLINK CONNECTOR ....................
  • Page 8 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 BOOT CONFIGURATION FORCED IN I2C BOOT ..................71 5.3.4 RESET DEFINITION ............................71 5.4.1 RESET BEHAVIOR ............................71 RESET SWITCHES AND TRIGGERS ......................71 5.4.2 SPI PROTOCOL ............................... 72 FPGA-DSP SPI PROTOCOL .......................... 72 5.5.1 5.5.2 FPGA- CDCE62005 (CLOCK GENERATOR) SPI PROTOCOL ..............
  • Page 9 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 List of Figures 1.1: B TMDXEVM6657L ......................12 IGURE LOCK IAGRAM OF TMDXEVM6657LE ......................13 1.2: B IGURE LOCK IAGRAM OF 1.3: TMDXEVM6657L .............................. 14 IGURE 1.4: TMDXEVM6657LE ............................15 IGURE 2.1: EVM B ............................
  • Page 10 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 List of Tables 2.1: TMS320C6657 M ..........................18 ABLE EMORY 2.2: B ........................22 ABLE ONFIGURATION ELECTION ........................23 2.3: PCA/PCB ABLE REVISION DESCRIPTION J5 ......................25 2.4: E ABLE MULATOR ELECTION USING 2.5: C...

  • Page 11: Overview

    The C6657 Lite EVM is a high performance, cost-efficient, standalone development platform that enables users to evaluate and develop applications for the Texas Instruments‟ TMS320C6657 Digital Signal Processor (DSP). The Evaluation Module (EVM) also serves as a hardware reference design platform for the TMS320C6657 DSP.

  • Page 12: Functional Overview

    The C6657 Lite EVM contains dual TMS320C6657 fixed point Digital Signal Processor. The TMS320C6657 device is based on the third-generation high-performance, advanced VelociTI™ very-long-instruction-word (VLIW) architecture, developed by Texas Instruments (TI), designed specifically for high density wireline / wireless media gateway infrastructure. This device is an excellent choice for IP border gateways, video transcoding and translation, video-server and intelligent voice and video recognition applications.

  • Page 13: Figure 1.2: Block Diagram Of Tmdxevm6657Le

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 The functional block diagram of TMDXEVM6657LE is shown in below figure: 2KB EEPROM (24LC02B-I/ST) AMC_SGMII x 1 AMC_McBSP_Data McBSP_Data LVL TXL (SN74AVC4T245) AMC_JTAG F_Px McBSP_AMC_EN# Gigbit Eth PHY (from FPGA) SGMII EMAC S_Px...

  • Page 14: Basic Operation

    USB cable supplied along with this EVM or through external emulator. The EVM comes with the Texas Instruments Multicore Software Development Kit (MCSDK) for SYS/BIOS OS. The BIOS MCSDK provides the core foundational building blocks that facilitate application software development on TI's high performance and multicore DSPs.

  • Page 15: Boot Mode And Boot Configuration Switch Setting

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Figure 1.4: TMDXEVM6657LE 1.4 Boot Mode and Boot Configuration Switch Setting The C6657 Lite EVM has 18 sliding DIP switches (Board Ref. SW3, SW5 and SW9) to determine boot mode, boot configuration, device number, Endian mode, CorePac PLL clock and PCIe mode selection.

  • Page 16: Power Supply

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 1.5 Power Supply C6657 Lite EVM can be powered from a single +12V / 2.5A DC (30W) external power supply connected to the DC power jack (DC_IN1)). Internally, +12V input is converted into required voltage levels using local DC-DC converters.

  • Page 17: Introduction To The C6657 Lite Evm Board

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 2. Introduction to the C6657 Lite EVM board This chapter provides an introduction and details of interfaces for the C6657 Lite EVM board. It contains: Memory Map EVM Boot mode and Boot configuration switch settings Board Revision ID JTAG - Emulation Overview Clock Domains...

  • Page 18: Table 2.1: Tms320C6657 Memory

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Table 2.1: TMS320C6657 Memory Map Page 18 / 90...
  • Page 19 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Page 19 / 90...
  • Page 20 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Page 20 / 90...
  • Page 21 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Page 21 / 90...

  • Page 22: Evm Boot Mode And Boot Configuration Switch Settings

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 2.2 EVM Boot mode and Boot Configuration Switch Settings C6657 Lite EVM has three configuration switches SW3, SW5 and SW9 that contain 18 values latched when reset is released. This occurs when power is applied the board, after the user presses the FULL_RESET push button or after a POR reset is requested from the MMC.

  • Page 23: Board Revision Id

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 2.3 Board Revision ID Board PCB (Printed Circuit Board) and PCA (Printed Circuit Assembly) revision are located below RJ-45 Jack in bottom silk, as shown in Figure 2.1. Table 3 describes the PCA/PCB revisions. Figure 2.1: EVM Board Revision Table 2.3: PCA/PCB revision description PCA Rev...

  • Page 24: Jtag - Emulation Overview

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 2.4 JTAG - Emulation Overview 2.4.1 JTAG – TMDXEVM6657L C6657 Lite EVM has on-board embedded JTAG emulation circuitry; hence user does not require any external emulator to connect EVM with Code Composer Studio. User can connect CCS with target DSP in EVM through USB cable supplied along with this board.

  • Page 25: Jtag - Tmdxevm6657Le

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 2.4.2 JTAG – TMDXEVM6657LE In TMDXEVM6657LE, high speed real time emulation can be performed without needing an external emulator as it has an integrated, system trace capable XDS560v2 Mezzanine Emulator mounted on its TI 60-pin JTAG header (EMU1).

  • Page 26: Xds560V2 Mezzanine Emulator Booting

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 2.4.2.1. XDS560v2 Mezzanine Emulator Booting When TMDXEVM6657LE is powered ON, the XDS560v2 Mezzanine Emulator starts booting. It takes approximately half minute to boot-up. The successful booting of XDS560v2 Mezzanine Emulator is indicated by following LEDs sequence: •...

  • Page 27: Clock Domains

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 2.5 Clock Domains The EVM incorporates variety of clocks to the TMS320C6657 as well as other devices which are configured automatically during the power up configuration sequence. The figure below illustrates the clocking for the system in EVM module.

  • Page 28: I2C Boot Eeprom / Spi Nor Flash

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 2.6 I2C Boot EEPROM / SPI NOR Flash The I2C modules on the TMS320C6657 may be used by the DSP to control local peripheral ICs (DACs, ADCs, etc.) or may be used to communicate with other controllers in a system or to implement a user interface. The I2C bus is connected to one EEPROM and to the 80-pin expansion header (TEST_PH1).

  • Page 29: Fpga

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 2.7 FPGA The FPGA (Xilinx XC3S200AN) controls the reset mechanism of the DSP and provides boot mode and boot configuration data to the DSP through SW3, SW5 and SW9. FPGA also provides the transformation of McBSP Frame Sync and Clock between AMC connector and the DSP.

  • Page 30: Ethernet Switch

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 2.8 Ethernet Switch The C6657 Lite EVM supports 1 port of SGMII interface which is multiplexed between Gigabit RJ-45 connector (Copper interface) and AMC finger (backplane SGMII interface) using a Gigabit Ethernet PHY Switch 88E1112 from Marvell.

  • Page 31: Serial Rapidio (Srio) Interface

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 2.9 Serial RapidIO (SRIO) Interface The C6657 Lite EVM supports high speed SERDES based Serial RapidIO (SRIO) interface. There are total 4 RapidIO ports available on C6657. All SRIO ports are routed to AMC edge connector on board. The figure below shows the RapidIO connections between the DSP and AMC edge connector.

  • Page 32: 16-Bit Asynchronous External Memory Interface (Emif-16) & Upp

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 2.11 16-bit Asynchronous External Memory Interface (EMIF-16) & UPP The C6657 Lite EVM EMIF-16 interface connects to one 1024Mbit (128MB) NAND flash device and 80-pin expansion header (TEST_PH1) on the C6657 Lite EVM. The EMIF16 module provides an interface between DSP and asynchronous external memories such as NAND and NOR flash.

  • Page 33: Hyperlink Interface

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 2.12 HyperLink Interface TMS320C6657 provides HyperLink bus for companion chip/die interfaces. This is a four lane SerDes interface designed to operate at 12.5 Gbps per lane and is used to connect with external accelerators. The interface includes the Serial Station Management Interfaces used to send power management and flow messages between devices.

  • Page 34: Mcbsp Interface

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 2.14 McBSP Interface McBSP module provides a glueless interface to common telecom serial data streams. The number of active serial links of McBSP0 and McBSP1 is four and they are connected to the AMC edge connector through a level shift IC to support 3.3V I/O on the C6657 Lite EVM.

  • Page 35: Uart Interface

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Table 2.7: McBSP Clock and Frame Sync Generation from TCLK Reg. FPGA Action Remarks Value A) McBSP_AMC_EN# = 0; B) Connect TDM_CLKA to SLCLKs, TxCLKs, RxCLKs; McBSP accessed over AMC Edge C) Connect TDM_CLKC to FSTs, FSRs.

  • Page 36: Module Management Controller (Mmc) For Ipmi

    The C6657 Lite EVM supports limited set of Intelligent Platform Management Interface (IPMI) commands using Module Management Controller (MMC) based on Texas Instruments MSP430F5435 mixed signal processor. The MMC will communicate with MicroTCA Carrier Hub (MCH) over IPMB (Intelligent Platform Management Bus) when inserted into AMC slot of a PICMG®...

  • Page 37: C6657 Lite Evm Board Physical Specifications

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 3. C6657 Lite EVM Board Physical Specifications This chapter describes the physical layout of the C6657 Lite EVM board and its connectors, switches and test points. It contains: Board Layout Connector Index Switches Test Points...

  • Page 38: Connector Index

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Figure 3.2: C6657 Lite EVM Board layout – Bottom view 3.2 Connector Index The C6657 Lite EVM Board has several connectors which provide access to various interfaces on the board. Table 3.1: C6657 Lite EVM Board Connectors Connector Pins...

  • Page 39: 560V2_Pwr1, Xds560V2 Mezzanine Power Connector

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 3.2.1 560V2_PWR1, XDS560v2 Mezzanine Power Connector 560V2_PWR1 is an 8 pin power connector for XDS560v2 mezzanine emulator board. The pin out for the connector is shown in the figure below: Table 3.2: XDS560v2 Power Connector pin out Pin # Signal Name...
  • Page 40 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Geographic Address 2 VCC12 +12V Power Ground Signal Ground Signal Ground Signal Ground Signal TDM_CLKD_P Telecom Clock D TDM_CLKD_N Telecom Clock D Ground Signal Ground Signal TDM_CLKC_P Telecom Clock C TDM_CLKC_N Telecom Clock C Ground Signal...

  • Page 41: Com1, Uart 3-Pin Connector

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 TDM_CLKB_P Telecom Clock B AMC_P9_SRIO2_RXP SRIO Port 1-RX TDM_CLKB_N Telecom Clock B AMC_P9_SRIO2_RXN SRIO Port 1-RX Ground Signal Ground Signal AMC_P8_SRIO1_TXP SRIO Port 0-TX AMC_P8_SRIO1_TXN SRIO Port 0-TX Ground Signal Ground Signal PS0# Presence 0...

  • Page 42: Dc_In1, Dc Power Input Jack Connector

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 3.2.5 DC_IN1, DC Power Input Jack Connector DV_IN1 is a DC Power-in Jack Connector for the stand-alone application of C6657 Lite EVM. It is a 2.5mm power jack with positive center tip polarity. Do not use this connector if EVM is inserted into MicroTCA chassis or AMC carrier back-plane.

  • Page 43: Hyperlink1, Hyperlink Connector

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Ground EMU1 Ground TRGRSTz 3.2.7 HyperLink1, Hyperlink Connector The EVM provides a HyperLink connection by a mini-SAS HD+ 4i connector. The connector contains 8 SERDES pairs and 4 sideband sets to carry full HyperLink signals. The connector is shown in Figure 3.4 and its pin out is shown in Table 3.8.

  • Page 44: J4 And J5, Emulation Path Selection Connector

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 3.2.8 J4 and J5, Emulation Path Selection Connector J4 and J5 are used to override preference to external emulator and provide an emulation path for AMC JTAG even when on-board XDS100 or external emulator is connected. Their connections are shown in tables below: Table 3.9: J4 Connector pin out Pin # Signal Name...

  • Page 45: Pmbus1, Pmbus Connector For Smart Reflex Control

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 3.2.10 PMBUS1, PMBUS Connector for Smart Reflex Control The TMS320C6657 DSP core power is supplied by a Smart-Reflex power controller UCD9222 with the Integrated FET Driver UCD7242. PMBUS1 provides a connection between UCD9222 and remote connection during development.

  • Page 46: Test_Ph1, Expansion Header (Emif-16, Spi, Gpio, Timer I/O, I2C, Mcbsp And Uart)

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 3.2.13 TEST_PH1, Expansion Header (EMIF-16, SPI, GPIO, Timer I/O, I2C, McBSP and UART) TEST_PH1 is an expansion header for several interfaces on the DSP. They are 16-bit EMIF, SPI, GPIO, Timer, I2C, McBSP and UART.

  • Page 47: Usb1, Mini Usb Connector

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 DSP_TIMI1/GPIO17 Timer input 1 DSP_McBSP0_RX McBSP Data In 0 DSP_TIMO1/GPIO19 Timer output 1 DSP_McBSP0_TX McBSP Data Out 0 DSP_SSPMISO/GPIO30 SPI data input DSP_McBSP1_RXCLK McBSP Receive Clk 1 DSP_SSPMOSI/GPIO31 SPI data output DSP_McBSP1_TXCLK McBSP Transmit Clk 1 DSP_SSPCS1/GPIO29...

  • Page 48: Dip And Pushbutton Switches

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 3.3 DIP and PushButton Switches The C6657 Lite EVM has three push button switches and three sliding actuator DIP switches. The RST_COLD1, RST_WARM1 and RST_FULL1 are push button switches while SW3, SW5 and SW9 are DIP switches. The function of each of the switches is listed in the table below: Table 3.17: C6657 Lite EVM Board Switches Switch...

  • Page 49: Sw4, Dsp Boot Mode

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Table 3.18: SW3, DSP Configuration Switch SW3 Position Description Default Value Function OFF - Big Endian mode LENDIAN 1(ON) ON - Little Endian mode BOOTMODE 0000 DSP Boot Mode Selection Pins BOOT DSP Device Configuration DEVICE...

  • Page 50: Test Points

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 3.4 Test Points The C6657 Lite EVM Board has 38 test points. The position of each test point is shown in the figure below: Figure 3.7: Board Test Points (Top) Figure 3.8: Board Test Points (Bottom) Page 50 / 90...

  • Page 51: System Leds

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Table 3.20: C6657 Lite EVM Board Test Points Test Point Signal MSP430 SMCLK MSP430 ACLK MSP430 MCLK TP134 DSP UART0 CTS TP135 DSP UART0 RTS TP12 DSP SYSCLKOUT TP31,TP32,TP33,TP34 Ground TP18 CVDD Supply TP19...

  • Page 52: Figure 3.9: Board Leds

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Figure 3.9: Board LEDs Additional LEDs on TMDXEVM6657LE board are highlighted in figure below and their description is listed in table 3.22. Figure 3.10: TMDXEVM6657LE Board Additional LEDs Page 52 / 90...

  • Page 53: Table 3.22: Tmdxevm6657Le B

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Table 3.22: TMDXEVM6657LE Board Additional LEDs LED# Color Description ON - DTC Ready D1 (Activity LED 1) OFF - DTC Not Ready ON - FPGA Programmed D2 (Activity LED 2) Yellow OFF - FPGA Not Programmed D3 (Activity LED 3)

  • Page 54: C6657 Lite Evm System Power Requirements

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 4. C6657 Lite EVM System Power Requirements This chapter describes the power design of C6657 Lite EVM board. It contains: Power Requirements Power Supply Distribution Power Supply Boot Sequence 4.1 Power Requirements Note that the power estimates stated in this section are maximum limits used in the design of the EVM.

  • Page 55: Figure 4.1: C6657 Lite Evm Power Consumption

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 VCC2V5 +2.50V 0.340A 0.85W PHY Analog & I/O Power PHY (88E112) 1.23W VCC1V2 +1.20V 0.320A 0.38W PHY Core Power VCC3V3_AUX +3.30V 0.200A 0.66W USB Emulation Power USB Emulator 0.79W (FT2232H) VCC1V8_AUX +1.80V 0.070A...

  • Page 56: Power Supply Distribution

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 4.2 Power Supply Distribution A high-level block diagram of the power supplies is shown in Figure 4.1. It is also shown in the schematic. In Figure 4.1, the Auxiliary power rails are always on after payload power is supplied. These regulators support all control, sequencing, and boot logic.

  • Page 57: Cvdd And Vcc1V0 Design

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 The TMS320C6657 core power is supplied using a dual digital controller coupled to a high performance FET driver IC. Additional DSP supply voltages are provided by discrete TI Swift power supplies. The TMS320C6657 supports a VID interface to enable Smart-Reflex®...

  • Page 58: Vcc3V3_Aux And Vcc1V5 Design

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 4.2.2 VCC3V3_AUX and VCC1V5 Design The VCC3V3_AUX and VCC1V5 power rails are regulated by two TI 6A Synchronous Step Down SWIFT™ Converters, TPS54620, to supply the peripherals and other power sources and the DSP DDR3 EMIF and DDR3 memory chips respectively.

  • Page 59: Vcc5 Design

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 4.2.3 VCC5 Design VCC5 L = 22uH C = 22uF x 1 TPS54321 Over all tolerance 5%, 10uF x 1 DC tolerance is 2.5% = 0.3 Figure 4.6: VCC5 Power Design on C6657 Lite EVM Output Capacitor Calculation Inductor Calculation = 1 / (2π*(V...
  • Page 60 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 delay time UCD9222 configuration file. Turn on VCC1V8 after VCC1V0 is stable VCC1V8 (DSP IO power) for 5ms. Unlock 1.8V outputs initiate CDCE62005#2 initiations CDCE62005 after VCC1V8 is stable for FPGA 1.8V outputs 5ms by de-asserting power down (PD#) pins.

  • Page 61: Figure 4.7: Initial Power Up Sequence Timing Diagram

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 VCC3V3_MP_AMC VCC3V3_MP VCC12 VCC3V_AUX_PG VCC3V3_AUX FPGA, FT2232, Misc FPGA VCC1V8_AUX FPGA, Eth PHY VCC1V2 VCC_5V_EN VCC5_PG XDS560v2 Mezzanine Card VCC5 T=10ms VCC2V5_EN T=5ms VCC2V5_PG Eth PHY VCC2V5 UCD9222_ENA1 UCD9222_PG1 CVDD1 T=5ms UCD9222_ENA2 UCD9222_PG1, UCD9222_PG...

  • Page 62: Figure 4.8: Power Down Sequence Timing Diagram

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 VCC3V3_MP_AMC VCC3V3_MP VCC12 FPGA, FT2232, Misc VCC3V3_AUX FPGA VCC1V8_AUX VCC1V2 FPGA, Eth PHY VCC_5V_EN XDS560v2 Mezzanine Card VCC5 VCC2V5_EN VCC2V5 Eth PHY UCD9222_ENA1 CVDD1 UCD9222_ENA2 VCC1V0 VCC1V8_EN1 VCC1V8 FPGA locks all output pins to DSP after VCC1V8_PG is de-asserted VCC1V5_EN DSP, DDR3...

  • Page 63: C6657 Lite Evm Fpga Functional Description

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 5. C6657 Lite EVM FPGA Functional Description This chapter describes the FPGA functionality of C6657 Lite EVM board. It contains: FPGA overview FPGA signals description Sequence of operation Reset definition SPI protocol CDCE62005 Programming Descriptions FPGA Configuration Registers...

  • Page 64: Table 5.1: Pin Type Notationi

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Table 5.1: Pin Type Notation Interpretation Pin Type Function Input Pin Output Pin Bidirectional Pin Differential Differential Pair Pins Internal Pull-Up Internal Pull-Down Table 5.2: C6657 Lite EVM FPGA Pin Description Pin Name I/O Type Description...
  • Page 65 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 5V Voltage Power Supply Enable: Enable for 5V VCC_5V_EN power rail. System Power Good Indication: Asserted by FPGA SYS_PGOOD to system when all power supplies are valid. Clock Configuration SPI Chip Select Enable: Connected to Clock Generator SPI_LE pin.
  • Page 66 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Reset to 88E1112 PHY: Used to reset the PHY device. PHY_RST# will be asserted during active PHY_RST# DSP_PORZ or DSP_RESETFULLZ period. The PHY_RST# logic also can be configured by the DSP accessed register.
  • Page 67 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Latch Enable for DSP Local Reset and NMI inputs: The default value is 1b and a register bit DSP_LRESETNMIENZ defines the state of this pin. DSP NMI: The default value is 1b and unlocked a DSP_NMIZ register bit defines the state of this pin.

  • Page 68: Sequence Of Operation

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 DSP Timer 0 Clock: FPGA provides a 24MHz clock to the DSP timer 0 input. During EVM Power-on or DSP_TIMI0 RESETFULLZ asserted period, FPGA will drive the PCIESSEN switch state to DSP for latching. DSP Timer 1 Clock: FPGA provides a 24MHz clock to the DSP timer 1 input.

  • Page 69: Power-On Sequence

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 5.3.3 Boot Configuration Timing 5.3.4 Boot Configuration Forced in I2C Boot 5.3.1 Power-On Sequence The following section provides details of the FPGA Power-On sequence of operation. 1. After the EVM 3.3V auxiliary voltage (VCC3V3_AUX_PG) is valid and stable, and FPGA design code is loaded, the FPGA is ready for the Power-On sequence of operation.

  • Page 70: Boot Configuration Timing

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 5.3.3 Boot Configuration Timing The boot configuration timing of the power-up and the RESETFULLz event are shown below. VCC0V75_PG T=5ms CLOCK2_PLL_LOCK T=5ms RESETz PORz T=5ms RESETFULLz T=3~4 48MHz RESETSTATz clock cycle DSP GPIOs All 0 Boot Config Switches value driven by FPGA...

  • Page 71: Boot Configuration Forced In I2C Boot

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 5.3.4 Boot Configuration Forced in I2C Boot Note: This workaround is only needed with PG1.0 samples of the TMS320C6657 DSP. For reliable PLL operation at boot-up, the FPGA will force the DSP to boot from the I2C by providing the boot configuration value as 0x0405 on the boot mode pins [12:0].

  • Page 72: Spi Protocol

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 almost everything. Soft Reset will behave like Hard Reset except that PCIe MMRs, EMIF16 MMRs, DDR3 EMIF MMRs, and External Memory contents are retained. Boot configurations are not latched by Warm Reset. Also, Warm Reset will not reset blocks supporting Reset Isolation when they are appropriately configured previously by application software.

  • Page 73: Figure 5.3: Spi Access From Tms320C6657 To Fpga (Write / High Level)

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Figure 5.3: SPI access from TMS320C6657 to FPGA (WRITE / high level) Figure 5.4: SPI access from TMS320C6657 to FPGA (WRITE) The below figures illustrate a DSP to FPGA SPI read operation. Figure 5.5: SPI access from TMS320C6657 to FPGA (READ / high level) Page 73 / 90...

  • Page 74: Fpga- Cdce62005 (Clock Generator) Spi Protocol

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Figure 5.6: SPI access from TMS320C6657 to FPGA (READ) 5.5.2 FPGA- CDCE62005 (Clock Generator) SPI Protocol The FPGA-Clock Generator SPI interface protocol is compatible to CDCE62005 SPI. The FPGA SPI bus clocks data in on the rising edge of DSP SPI Clock.

  • Page 75: Fpga Configuration Registers

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 5.6 FPGA Configuration Registers The TMS320C6657 DSP communicates with the FPGA configuration registers through the SPI interface. These registers are addressed by memory mapped location and defined by the DSP SPI chip enable setting. The following tables list the FPGA configuration registers and the respective descriptions.

  • Page 76: Fpga Configuration Registers Descriptions

    Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 CLK-GEN 2 Command Byte 2 CLK-GEN 2 Command Byte 3 CLK-GEN 2 Read Data Byte 0 CLK-GEN 2 Read Data Byte 1 CLK-GEN 2 Read Data Byte 2 CLK-GEN 2 Read Data Byte 3 1Fh~2Ch Reserved 3Fh~30h...
  • Page 77 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Page 77 / 90...
  • Page 78 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Register Address: SPI Base + 03h Register Name: FPGA Revision ID (Low Byte) Register Default Value: 00h* Attribute: Read Only Description Read/Write FPGA Device ID (High Byte) This register combined with the offset 02h register specifies FPGA device specific revision identifier.
  • Page 79 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 BM GPIO 07: This bit reflects the state of the BM general purpose input signal GPIO 07 and writes will have no effect. 0 : BM GPIO 07 state is low 1 : BM GPIO 07 state is high SPI Base + 05h Register Address:...
  • Page 80 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Register Address: SPI Base + 06h Register Name: DSP GPI Status (07-00 Low Byte) Register Default Value: ------ Attribute: Read Only Description Read/Write DSP GPIO 00: This bit reflects the state of the DSP general purpose input signal GPIO 00 and writes will have no effect.
  • Page 81 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Register Address: SPI Base + 07h Register Name: DSP GPI Status (15-08 High Byte) Register Default Value: Attribute: Read Only Description Read/Write DSP GPIO 08: This bit reflects the state of the DSP general purpose input signal GPIO 08 and writes will have no effect.
  • Page 82 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Register Address: SPI Base + 08h Register Name: Debug LED Register Default Value: Attribute: Read/Write Description Read/Write DEBUG_LED 1: This bit can be updated by the DSP software to drive a high or low value on the debug LED 1 pin.
  • Page 83 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 MMC_BOOTCOMP: This bit reflects DSP BOOTCOMPLETE state and FPGA will drive the same logic value on the MMC_BOOTCOMP pin (to MMC). 0: State is low and FPGA drives MMC_ BOOTCOMP low to MMC 1: State is high and the FPGA drives MMC_ BOOTCOMP high to MMC Reserved Register Address:...
  • Page 84 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 DSP_RESETSTAT#: This bit reflects the DSP_RESETSTAT# state. 0: DSP_RESETSTAT# state is low 1: DSP_RESETSTAT# state is high TRGRSTZ: This bit reflects the TRGRSTZ state. 0: TRGRSTZ state is low 1: TRGRSTZ state is high PCIESSEN: This bit reflects the PCIESSEN switch state.
  • Page 85 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 PCA9306_EN: This bit can be updated by the DSP software to drive a high or low value on the PCA9306_EN pin (RFU) 0 : PCA9306_EN drives low (Default) 1 : PCA9306_EN drives high Reserved Register Address: SPI Base + 0Dh...
  • Page 86 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Register Address: SPI Base + 0Fh Register Name: Scratch Register Default Value: Attribute: Read/Write Description Read/Write Scratch Data Register Address: SPI Base + 10h Register Name: CLK-GEN 2 Control Register Default Value: Attribute: Read/Write...
  • Page 87 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Register Address: SPI Base + 14h Register Name: CLK-GEN 2 Command Byte 0 Register Default Value: Attribute: Read/Write Description Read/Write This register specifies the update SPI command byte 0 to the CDCE62005 Clock Generator #2 3-0 : SPI command address field bit 3 to bit 0 7-4 : SPI command data field bit 3 to bit 0...
  • Page 88 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Register Address: SPI Base + 19h Register Name: CLK-GEN 2 Read Data Byte 1 Register Default Value: Attribute: Read/Write Description Read/Write This register reflects the read back data byte 1 from the CDCE62005 Clock Generator #2 for responding a host SPI Read Command.
  • Page 89 Technical Reference Manual TMDXEVM6657L TMDXEVM6657LE SPRUHG7 - Revised August 2012 Register Address: SPI Base + 50h Register Name: CLK-MUX Selection Control Register Default Value: Attribute: Read/Write Description Read/Write CLK_MUX_SEL: This bit can be updated by the DSP software to drive a high or low value on the CLK_MUX_SEL pin.
  • Page 90 IMPORTANT NOTICE Texas Instruments Incorporated and its subsidiaries (TI) reserve the right to make corrections, modifications, enhancements, improvements, and other changes to its products and services at any time and to discontinue any product or service without notice. Customers should obtain the latest relevant information before placing orders and should verify that such information is current and complete.
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