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eInfochips TMDXEVM6657LE
Texas Instruments eInfochips TMDXEVM6657LE Manuals
Manuals and User Guides for Texas Instruments eInfochips TMDXEVM6657LE. We have
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Texas Instruments eInfochips TMDXEVM6657LE manual available for free PDF download: Technical Reference Manual
Texas Instruments eInfochips TMDXEVM6657LE Technical Reference Manual (91 pages)
Brand:
Texas Instruments
| Category:
Motherboard
| Size: 3 MB
Table of Contents
Table of Contents
6
1 Overview
11
Key Features
11
Functional Overview
12
Figure 1.1: Block Diagram of Tmdxevm6657L
12
Figure 1.2: Block Diagram of Tmdxevm6657Le
13
Basic Operation
14
Boot Mode and Boot Configuration Switch Setting
15
Figure 1.4: Tmdxevm6657Le
15
Power Supply
16
2 Introduction to the C6657 Lite Evm Board
17
Memory Map
17
Table 2.1: Tms320C6657 Memory
18
Evm Boot Mode and Boot Configuration Switch Settings
22
Table 2.2: Boot Configuration
22
Board Revision ID
23
Figure 2.1: Evm Board Revision
23
Table 2.3: Pca/Pcb Revision Description
23
Jtag - Emulation Overview
24
Jtag - Tmdxevm6657L
24
Figure 2.2: Tmdxevm6657L Jtag Emulation
24
Jtag - Tmdxevm6657Le
25
Figure 2.3: Tmdxevm6657Le Jtag Emulation
25
Table 2.4: Emulator Selection Using
25
Xds560V2 Mezzanine Emulator Booting
26
Clock Domains
27
Figure 1.3: Tmdxevm6657L
27
Figure 2.3: C6657 Lite Evm Clock Domains
27
Table 2.5: Clock Configuration
27
I2C Boot Eeprom / Spi nor Flash
28
Figure 2.4: C6657 Lite Evm Clock Domains
28
Fpga
29
Figure 2.5: C6657 Lite Evm Fpga Connections
29
Ethernet Switch
30
Figure 2.6: C6657 Lite Evm Ethernet Phy Routing
30
Table 2.6: Led Indication
30
Serial Rapidio (Srio) Interface
31
Ddr3 External Memory Interface
31
Figure 2.7: C6657 Lite Evm Srio Port Connections
31
Figure 2.8: C6657 Lite Evm Ddr3 Interface
31
16-Bit Asynchronous External Memory Interface (Emif-16) & Upp
32
Figure 2.9: C6657 Lite Evm Emif16 Interface
32
Hyperlink Interface
33
Pcie Interface
33
Figure 2.10: C6657 Lite EVM Hyperlink Interface
33
Figure 2.11: C6657 Lite EVM Pcie Interface
33
Mcbsp Interface
34
Figure 2.12: C6657 Lite EVM Mcbsp Interface
34
Figure 2.13: C6657 Lite EVM Mcbsp Clock Generation by FPGA
34
Uart Interface
35
Figure 2.14: C6657 Lite Evm Uart Connections
35
Table 2.7: M Cbsp Clock Andf
35
Module Management Controller (MMC) for Ipmi
36
Expansion Header
36
Figure 2.15: C6657 Lite Evm MMC Connections for Ipmi
36
3 C6657 Lite Evm Board Physical Specifications
37
Board Layout
37
Figure 3.1: C6657 Lite Evm Board Assembly Layout - Top View
37
Connector Index
38
Figure 3.2: C6657 Lite Evm Board Layout - Bottom View
38
Table 3.1: C6657 Lite Evm Board
38
560V2_Pwr1, Xds560V2 Mezzanine Power Connector
39
Amc1, Amc Edge Connector
39
Table 3.2: Xds560 V 2 Powerc
39
Table 3.3: Amc Edge Connector
39
Com1, Uart 3-Pin Connector
41
Com_Sel1, Uart Route Select Connector
41
Figure 3.3: Com_Sel1 Jumper Settings
41
Table 3.4: Uart Connector Pin out
41
Table 3.5: Uart Path Selectc
41
Dc_In1, DC Power Input Jack Connector
42
Emu1, Ti 60 Pin Dsp Jtag Connector
42
Table 3.6: Dc_In1 Connector Pin out
42
Table 3.7: Dsp Jtag C
42
Hyperlink1, Hyperlink Connector
43
Figure 3.4: Hyperlink Connector
43
Table 3.8: Dsp Jtag C
43
J4 and J5, Emulation Path Selection Connector
44
Lan1, Ethernet Connector
44
Table 3.9: J4 Connector Pin out
44
Table 3.10: J5 Connector Pin out
44
Table 3.11: Ethernetc
44
Pmbus1, Pmbus Connector for Smart Reflex Control
45
Tap_Fpga1, Fpga Jtag Connector (for Factory Use Only)
45
Sbw_Mmc1, Msp430 Spybiwire Connector (for Factory Use Only)
45
Table 3.12: Pmbus Connector
45
Table 3.13: Fpga Jtag Header
45
Table 3.14: Msp430 Spy B I Wire
45
Test_Ph1, Expansion Header (Emif-16, Spi, Gpio, Timer I/O, I2C, Mcbsp and Uart)
46
Table 3.15: 80- Pin Expansionh
46
Usb1, Mini Usb Connector
47
Table 3.16: Mini -Usb C
47
Dip and Pushbutton Switches
48
Rst_Cold1, Cold Reset
48
Rst_Full1, Full Reset
48
Rst_Warm1, Warm Reset
48
Sw3, Dsp Configuration
48
Figure 3.5: Sw3 Default Settings
48
Table 3.17: C6657 Lite Evm B
48
Sw4, Dsp Boot Mode
49
Figure 3.6: Sw5 Default Settings
49
Table 3.18: Sw3, Dsp Configuration
49
Table 3.19: Sw4, Dsp Boot Mode
49
Test Points
50
Figure 3.7: Board Test Points (Top)
50
Figure 3.8: Board Test Points (Bottom)
50
System Leds
51
Table 3.20: C6657 Lite Evm B
51
Table 3.21: C6657 Lite Evm B
51
Figure 3.9: Board Leds
52
Figure 3.10: TMDXEVM6657LE Board Additional Leds
52
Table 3.22: Tmdxevm6657Le B
53
4 C6657 Lite Evm System Power Requirements
54
Power Requirements
54
Table 4.1: Current Consumption on
54
Figure 4.1: C6657 Lite Evm Power Consumption
55
Power Supply Distribution
56
Figure 4.2: C6657 Lite Evm Power Generation Topology
56
CVDD and Vcc1V0 Design
57
Figure 4.3: CVDD and Vcc1V0 Design on C6657 Lite Evm
57
Vcc3V3_Aux and Vcc1V5 Design
58
Figure 4.4: Vcc3V3_Aux Design on C6657 Lite Evm
58
Figure 4.5: Vcc1V5 Power Design on C6657 Lite Evm
58
Vcc5 Design
59
Power Supply Boot Sequence
59
Figure 4.6: Vcc5 Power Design on C6657 Lite Evm
59
Table 4.2: Power - up and down Timing on
59
Figure 4.7: Initial Power up Sequence Timing Diagram
61
Figure 4.8: Power down Sequence Timing Diagram
62
5 C6657 Lite Evm Fpga Functional Description
63
Fpga Overview
63
Fpga Signals Description
63
Table 5.1: Pin Type Notationi
64
Table 5.2: C6657 Lite Evm Fpga P
64
Sequence of Operation
68
Power-On Sequence
69
Power off Sequence
69
Boot Configuration Timing
70
Figure 5.1: Power-On Reset Boot Configuration Timing
70
Figure 5.2: Reset-Full Switch/Trigger Boot Configuration Timing
70
Boot Configuration Forced in I2C Boot
71
Reset Definition
71
Reset Behavior
71
Reset Switches and Triggers
71
Spi Protocol
72
Fpga-Dsp Spi Protocol
72
Figure 5.3: SPI Access from TMS320C6657 to FPGA (WRITE / High Level)
73
Figure 5.4: Spi Access from Tms320C6657 to Fpga (Write)
73
Figure 5.5: SPI Access from TMS320C6657 to FPGA (READ / High Level)
73
Fpga- Cdce62005 (Clock Generator) Spi Protocol
74
Figure 5.6: Spi Access from Tms320C6657 to Fpga (Read)
74
Figure 5.7: Spi Access from Fpga to Cdce62005 (Write)
74
Figure 5.8: Spi Access from Fpga to Cdce62005 (Read)
74
Fpga Configuration Registers
75
Fpga Configuration Registers Summary
75
Table 5.3: C6657 Lite Evm Fpga P
75
Fpga Configuration Registers Descriptions
76
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