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ZS550
5–7
Display
Description
status
Off
OERATE mode (error-free operation);
The busmaster is in cyclic I/O data transfer
CLEAR mode, cause:
D controller in Stop
D controller in CLAB (disable outputs)
The busmaster is in cyclic I/O data transfer
For the outputs 00H will be transferred (outputs canceled)
New master parameter set (MPS) is loaded
OFFLINE mode
The busmaster is offline
No or only invalid MPS available
Bootstrap initialization (after off/on) is active
The busmaster tries to start with the existing MPS
The initialization phase will be stopped if:
D an error (hardware, address assignment, MPS, etc.) is pending
D all slaves can be reached without an error
D the PLC_Stop_Time is expired
At least 1 slave indicates a configuration error
At least 1 slave is not reachable or not ready for cyclic data transfer
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Bus error
Busmaster cannot access the bus (no idle state level)
Possible causes:
D Short circuit on the field bus
D Terminating resistance not switched on
D Terminating resistance has no voltage
System error in busmaster
1070 072 263-101 (01.08) GB
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