In-Service Register (Inserv, Offset 2Ch); (Master Mode) - AMD AM186EM User Manual

7.3.9

In-Service Register (INSERV, Offset 2Ch)

(Master Mode)

The Am186EM and Am188EM microcontrollers define three new bits to report the in-service
state of INT4, the Virtual Watchdog Timer, and the asynchronous serial port. The format
of the modified In-Service register is shown in Figure 7-12.
The bits in the INSERV register are set by the interrupt controller when the interrupt is
taken. Each bit in the register is cleared by writing the corresponding interrupt type to the
End-of-Interrupt (EOI) register. See Table 7-1 on page 7-3.
When an in-service bit is set, the microcontroller will not generate an interrupt request for
the associated source, preventing an interrupt from interrupting itself if interrupts are
enabled in the ISR. Special fully nested mode allows the INT1–INT0 requests to circumvent
this restriction for the INT0 and INT1 sources.
Figure 7-12 In-Service Register (INSERV, offset 2Ch)
The INSERV register is set to 0000h on reset.
Bits 15–11: Reserved
Bit 10: Serial Port Interrupt In-Service (SPI)—This bit indicates the in-service state of
the asynchronous serial port.
Bit 9: Watchdog Timer Interrupt In-Service (WD)—This bit indicates the in-service state
of the Watchdog Timer.
Bits 8–4: Interrupt In-Service (I4–I0)—These bits indicate the in-service state of the
corresponding INT pin.
Bits 3–2: DMA Channel Interrupt In-Service (D1–D0)—These bits indicate the in-service
state of the corresponding DMA channel.
Bit 1: Reserved
Bit 0: Timer Interrupt In-Service (TMR)—This bit indicates the state of the in-service timer
interrupts. This bit is the logical OR of all the timer interrupt status bits. When set to a 1,
this bit indicates that the corresponding timer interrupt status bit is in-service.
7-22
7
15
Reserved
SPI I4
WD I3
Interrupt Control Unit
0
I2 I0 D0 TMR
I1 D1 Res