Push Buttons; Cypress Quad Spi Nor Flash; Bill Of Materials - Cypress CY8CPROTO-062S3-4343W Manual

3.2.8

Push Buttons

The PSoC 62S3 Wi-Fi BT Prototyping Board has a reset button and 1 user button. The reset button
(SW1) is connected to the XRES pin of the PSoC 6 MCU and is used to reset the device. One user
button (SW2) is connected to pin P0[4] of the PSoC 6 MCU. In addition, the Mode selection button
SW3 is connected to the PSoC 5LP device for programming mode selection (Refer to the
User Guide for details). All the buttons connect to ground on activation (active low).
The CY8CMOD-062S3-4343W provides pull-up for the XRES line of PSoC 6 MCU.
Figure 3-11. Schematics of Push Buttons
User Button /
Hibernate Wakeup
VBACKUP
1
USER_BTN_1
2
3.2.9

Cypress Quad SPI NOR Flash

The PSoC 62S3 Wi-Fi BT Prototyping Board has a Cypress NOR flash memory (S25FL512SAGM-
FIR10) of 512 Mbit capacity. The NOR Flash is connected to the Quad SPI interface of the
PSoC 6 MCU. The NOR device can be used for both data and code memory with execute-in-place
(XIP) support and encryption.
Figure 3-12. Schematics of QSPI Flash
VCC_FLASH
Quad SPI Flash Memory Section
QSPI_IO3
FLASH_RST_L
FLASH_SS_L
QSPI_IO1
VCC_IO_FLASH
R65
10K
R8
10K
No Load
VTARG
R34
No Load
R39
3.3

Bill of Materials

Refer to the BOM files in the
CY8CPROTO-062S3-4343W PSoC 62S3 Wi-Fi BT Prototyping Kit Guide, Doc. # 002-28070 Rev. *A
R48
XRES_L_MCU
10K
4
SW2
3
SKRPACE010
U1
1 16
HOLD /IO3 SCK
2 15
VCC SI /IO0
3 14
RESET /RFU DNU_7
4 13
DNU_1 DNU_6
5 12
DNU_2 DNU_5
6 11
DNU_3 DNU_4
7 10
CS VSS
8 9
SO/IO1 WP /IO2
S25FL512SAGMFIR10
VCC_IO_FLASH
ARD_D4
ARD_D5
FLASH_SS_L
VCC_FLASH
FLASH_INT_L
VCC_3V3
VCC_FLASH
0 OHM R40 0 OHM
VCC_IO_FLASH
0 OHM
kit webpage.
Reset Button
VDDD
R56 4.7K
No Load
1 4
SW1
2 3
SKRPACE010
C46
0.1uF
No Load
VCC_IO_FLASH
QSPI_SCK
QSPI_IO0
FLASH_INT_L
QSPI_IO2
FLASH_RST_L
R4 0 OHM
No Load
FLASH_INT_L
R6 0 OHM
No Load
VCC_IO_FLASH
C1 C2 C3
1uF 0.1uF 1uF
10V 16V 10V
Mode Switch
1 4
P5LP1_2
SW3
2 3
SKRPACE010
C4
0.1uF
16V
Hardware
KitProg3
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