Cypress CY8C28 series Manuals

Manuals and User Guides for Cypress CY8C28 series. We have 2 Cypress CY8C28 series manuals available for free PDF download: Technical Reference Manual, Manual

Cypress CY8C28 series Technical Reference Manual (571 pages)

Programmable System-on-Chip

Brand: Cypress | Category: Single board computers | Size: 5 MB

Contents Overview

4
- Table of Contents
  4
- Document Organization
  22
- Section A: Overview
  22
- Top Level Architecture
  23
- Psoc Core
  23
- Digital System
  23
- Analog System
  23
- System Resources
  23
- Psoc Device Characteristics
  25
- Psoc Device Distinctions
  26
- Getting Started
  27
- Support
  27
- Product Upgrades
  27
- Development Kits
  27
- Document History
  27
- Numeric Naming
  28
- Units of Measure
  28
- Documentation Conventions
  28
- Register Conventions
  28
- Acronyms
  29
- Pin Information
  30
- Pinouts for the Cy8C28Xxx
  30
- 20-Pin Part Pinouts
  31
- 28-Pin Part Pinouts
  32
- 44-Pin Part Pinouts
  33
- 48-Pin Part Pinouts
  34
- 56-Pin Part Pinout
  35
- Interpreting the Core Documentation
  36
- Section B: Psoc ® Core
  36
- Top Level Core Architecture
  36
- Core Register Summary
  37
- CPU Core (M8C)
  40
- Overview
  40
- Internal Registers
  40
- Address Spaces
  40
- Instruction Set Summary
  41
- Two-Byte Instructions
  43
- One-Byte Instructions
  43
- Instruction Formats
  43
- Three-Byte Instructions
  44
- Addressing Modes
  44
- Source Immediate
  44
- Source Direct
  45
- Source Indexed
  45
- Destination Direct
  46
- Destination Indexed
  46
- Destination Direct Source Immediate
  46
- Destination Indexed Source Immediate
  47
- Destination Direct Source Direct
  47
- Source Indirect Post Increment
  48
- Destination Indirect Post Increment
  48
- Register Definitions
  49
- CPU_F Register
  49
- Supervisory ROM (SROM)
  50
- Architectural Description
  50
- Swbootreset Function
  51
- SROM Function Descriptions
  51
- Additional SROM Feature
  51
- Hwbootreset Function
  52
- Readblock Function
  52
- Writeblock Function
  53
- Eraseblock Function
  53
- Protectblock Function
  53
- Tableread Function
  53
- Calibrate0 Function
  54
- Checksum Function
  54
- Eraseall Function
  54
- Calibrate1 Function
  55
- Writeandverify Function
  55
- Register Definitions
  55
- FLS_PR1 Register
  55
- Clocking Strategy
  57
- DELAY Parameter
  57
- CLOCK Parameter
  57
- Basic Paging
  58
- Architectural Description
  58
- RAM Paging
  58
- Current
  59
- Stack Operations
  59
- MVI Instructions
  59
- Interrupts
  59
- Index Memory
  60
- Register Definitions
  61
- Tmp_Drx Registers
  61
- CUR_PP Register
  61
- STK_PP Register
  62
- IDX_PP Register
  62
- MVR_PP Register
  62
- MVW_PP Register
  63
- CPU_F Register
  63
- MVR_PP Register
  63
- MVW_PP Register
  64
- CPU_F Register
  64
- Interrupt Controller
  66
- Architectural Description
  66
- Posted Versus Pending Interrupts
  67
- Application Description
  68
- Register Definitions
  69
- Int_Clrx Registers
  69
- INT_CLR0 Register
  69
- INT_CLR1 Register
  70
- INT_CLR2 Register
  70
- INT_CLR3 Register
  70
- Int_Mskx Registers
  71
- INT_MSK3 Register
  71
- INT_MSK2 Register
  71
- INT_MSK0 Register
  71
- INT_MSK1 Register
  72
- INT_VC Register
  72
- CPU_F Register
  73
- Digital I/O
  74
- Global I/O
  74
- Architectural Description
  74
- General Purpose I/O (GPIO)
  74
- Analog Input
  75
- GPIO Block Interrupts
  76
- Register Definitions
  77
- Prtxdr Registers
  77
- Prtxie Registers
  77
- Prtxgs Registers
  77
- Prtxdmx Registers
  78
- Prtxicx Registers
  78
- Architectural Description
  80
- Analog Output Drivers
  80
- Register Definitions
  81
- ABF_CR0 Register
  81
- Internal Main Oscillator (IMO)
  82
- Architectural Description
  82
- Application Description
  82
- Trimming the IMO
  82
- Engaging Slow IMO
  82
- OSC_CR2 Register
  83
- Register Definitions
  83
- CPU_SCR1 Register
  83
- IMO_TR Register
  84
- IMO_TR1 Register
  84
- Internal Low Speed Oscillator (ILO)
  86
- Architectural Description
  86
- Register Definitions
  86
- ILO_TR Register
  86
- External Crystal Oscillator (ECO)
  88
- Architectural Description
  88
- ECO External Components
  89
- Register Definitions
  90
- CPU_SCR1 Register
  90
- OSC_CR0 Register
  91
- OSC_CR2 Register
  92
- ECO_TR Register
  92
- Phase-Locked Loop (PLL)
  94
- Architectural Description
  94
- Register Definitions
  94
- OSC_CR0 Register
  95
- OSC_CR2 Register
  96
- Sleep and Watchdog
  98
- Architectural Description
  98
- 32 Khz Clock Selection
  98
- Sleep Timer
  98
- Application Description
  99
- Register Definitions
  100
- INT_MSK0 Register
  100
- RES_WDT Register
  100
- CPU_SCR1 Register
  101
- CPU_SCR0 Register
  102
- OSC_CR0 Register
  103
- OSC_CR2 Register
  104
- ILO_TR Register
  104
- ECO_TR Register
  105
- Timing Diagrams
  105
- Sleep Sequence
  105
- Wakeup Sequence
  106
- Bandgap Refresh
  108
- Watchdog Timer
  108
- Power Consumption
  109
- Section C: Register Reference
  110
- Register General Conventions
  110
- Register Naming Conventions
  110
- Register Mapping Tables
  110
- Cy8C28X03 Register Maps
  111
- Register Map Bank 0 Table: User Space
  111
- Register Map Bank 1 Table: Configuration Space
  112
- Cy8C28X13 Register Maps
  113
- Register Map Bank 0 Table: User Space
  113
- Register Map Bank 1 Table: Configuration Space
  114
- Cy8C28X23 Register Maps
  115
- Register Map Bank 0 Table: User Space
  115
- Register Map Bank 1 Table: Configuration Space
  116
- Cy8C28X33 Register Maps
  117
- Register Map Bank 0 Table: User Space
  117
- Register Map Bank 1 Table: Configuration Space
  118
- Cy8C28X43 Register Maps
  119
- Register Map Bank 0 Table: User Space
  119
- Register Map Bank 1 Table: Configuration Space
  120
- Cy8C28X45 Register Maps
  121
- Register Map Bank 0 Table: User Space
  121
- Register Map Bank 1 Table: Configuration Space
  122
- Cy8C28X52 Register Maps
  123
- Register Map Bank 0 Table: User Space
  123
- Register Map Bank 1 Table: Configuration Space
  124
- Maneuvering Around the Registers
  126
- Register Details
  126
- Register Conventions
  127
- Register Naming Conventions
  127
- Bank 0 Registers
  128
- Prtxdr
  128
- Prtxie
  129
- Prtxgs
  130
- Prtxdm2
  131
- Dxcxxdr0
  132
- Dxcxxdr1
  133
- Dxcxxdr2
  134
- Dxcxxcr0 (Timer Control:000)
  135
- Dxcxxcr0 (Counter Control:001)
  136
- Dxcxxcr0 (Dead Band Control:100)
  137
- Dxcxxcr0 (CRCPRS Control:010)
  138
- Dxcxxcr0 (PWMDBL Control:011)
  139
- Dccxxcr0 (SPIM Control:0-110)
  141
- Dccxxcr0 (SPIS Control:1-110)
  142
- Dxcxxcr0 (DSM Control:111)
  143
- Dccxxcr0 (UART Transmitter Control)
  144
- Dccxxcr0 (UART Receiver Control)
  145
- Amx_In
  146
- Amux_Cfg
  147
- Clk_Cr3
  148
- Arf_Cr
  149
- Cmp_Cr0
  150
- Asy_Cr
  151
- Cmp_Cr1
  152
- Sadc_Dh
  154
- Sadc_Dl
  155
- Tmp_Drx
  156
- Accxxcr3
  157
- Accxxcr0
  158
- Accxxcr1
  160
- Accxxcr2
  161
- Ascxxcr0
  162
- Ascxxcr1
  163
- Ascxxcr2
  164
- Ascxxcr3
  165
- Asdxxcr0
  166
- Asdxxcr1
  167
- Asdxxcr2
  168
- Asdxxcr3
  169
- Decx_Dh
  170
- Decx_Dl
  171
- Mulx_X
  172
- Mulx_Y
  173
- Mulx_Dh
  174
- Mulx_Dl
  175
- Macx_X/Accx_Dr1
  176
- Macx_Y/Accx_Dr0
  177
- Macx_Cl0/Accx_Dr3
  178
- Macx_Cl1/Accx_Dr2
  179
- Rdixri
  180
- Rdixsyn
  181
- Rdixis
  182
- Rdixlt0
  183
- Rdixlt1
  185
- Rdixro0
  187
- Rdixro1
  188
- Rdixdsm
  189
- Cur_Pp
  190
- Stk_Pp
  191
- Idx_Pp
  192
- Mvr_Pp
  193
- Mvw_Pp
  194
- I2Cx_Cfg
  195
- I2Cx_Scr
  196
- I2Cx_Dr
  198
- I2Cx_Mscr
  199
- Int_Clr0
  200
- Int_Clr1
  202
- Int_Clr2
  204
- Int_Clr3
  205
- Int_Msk3
  207
- Int_Msk2
  208
- Int_Msk0
  209
- Int_Msk1
  210
- Int_Vc
  211
- Res_Wdt
  212
- Dec_Cr0
  213
- Dec_Cr1
  214
- Cpu_F
  215
- Idacx_D
  216
- Cpu_Scr1
  217
- Cpu_Scr0
  218
- Bank 1 Registers
  219
- Prtxdm0
  219
- Prtxdm1
  220
- Prtxic0
  221
- Prtxic1
  222
- Dxcxxfn
  223
- Dxcxxin
  225
- Dxcxxou
  227
- Dxcxxcr1 (Timer Control:000)
  229
- Dxcxxcr1 (Counter Control:001)
  230
- Dxcxxcr1 (CRCPRS Control:010)
  231
- Dxcxxcr1 (PWMDBL Control:011)
  232
- Dxcxxcr1 (Dead Band Control:100)
  233
- Dxcxxcr1 (SPIM Control:0-110)
  234
- Dxcxxcr1 (SPIS Control:0-110)
  235
- Dxcxxcr1 (DSM Control:111)
  236
- Clk_Cr0
  237
- Clk_Cr1
  238
- Abf_Cr0
  239
- Amd_Cr0
  240
- Cmp_Go_En
  241
- Cmp_Go_En1
  242
- Amd_Cr1
  243
- Alt_Cr0
  244
- Alt_Cr1
  245
- Clk_Cr2
  246
- Amux_Cfg1
  247
- Sadc_Tscr0
  248
- Sadc_Tscr1
  249
- Ace_Amd_Cr0
  250
- Ace_Amx_In
  251
- Ace_Cmp_Cr0
  252
- Ace_Cmp_Cr1
  253
- Ace_Cmp_Gi_En
  254
- Ace_Alt_Cr0
  255
- Ace_Abf_Cr0
  256
- Acexxcr1
  257
- Acexxcr2
  258
- Asexxcr0
  259
- Sadc_Tscmpl
  260
- Sadc_Tscmph
  261
- Ace_Amd_Cr1
  262
- Ace_Pwm_Cr
  263
- Ace_Adcx_Cr
  264
- Ace_Clk_Cr0
  265
- Ace_Clk_Cr1
  266
- Ace_Clk_Cr3
  267
- Decx_Cr0
  268
- Dec_Cr3
  269
- Dec_Cr4
  270
- Dec_Cr5
  271
- Gdi_O_In_Cr
  272
- Gdi_E_In_Cr
  273
- Gdi_O_Ou_Cr
  274
- Gdi_E_Ou_Cr
  275
- Rtc_H
  276
- Rtc_M
  277
- Rtc_S
  278
- Rtc_Cr
  279
- Sadc_Cr0
  280
- Sadc_Cr1
  281
- Sadc_Cr2
  282
- Sadc_Cr3
  283
- Sadc_Cr4
  284
- I2Cx_Addr
  285
- Amux_Clk
  286
- Gdi_O_In
  287
- Gdi_E_In
  288
- Gdi_O_Ou
  289
- Gdi_E_Ou
  290
- Decx_Cr
  291
- Mux_Crx
  292
- Idac_Cr1
  293
- Osc_Go_En
  294
- Osc_Cr4
  295
- Osc_Cr3
  296
- Osc_Cr0
  297
- Osc_Cr1
  298
- Osc_Cr2
  299
- Vlt_Cr
  300
- Vlt_Cmp
  301
- Adcx_Tr
  302
- Idac_Mode
  303
- Imo_Tr
  304
- Ilo_Tr
  305
- Bdg_Tr
  306
- Eco_Tr
  307
- Imo_Tr1
  308
- Fls_Pr1
  309
- Idac_Cr0
  310
- Section D: Digital System
  312
- Top-Level Digital Architecture
  312
- Interpreting the Digital Documentation
  312
- Digital Register Summary
  313
- Global Digital Interconnect (GDI)
  318
- Architectural Description
  318
- 20-Pin Global Interconnect
  319
- 28-Pin Global Interconnect
  320
- 44-Pin Global Interconnect
  321
- 48-Pin Global Interconnect
  322
- 56-Pin Global Interconnect
  323
- Register Definitions
  323
- Gdi_X_In Registers/Gdi_X_In_Cr Registers
  323
- Gdi_X_Ou/Gdi_X_Ou_Cr Registers
  324
- Architectural Description
  326
- Array Digital Interconnect (ADI)
  326
- Row Digital Interconnect (RDI)
  328
- Architectural Description
  328
- Register Definitions
  330
- Rdixri Register
  330
- Rdixsyn Register
  331
- Rdixis Register
  332
- Rdixltx Registers
  333
- Rdixro1 Register
  334
- Rdixro0 Register
  334
- Rdixrox Registers
  334
- Timing Diagram
  335
- Rdixdsm Register
  335
- Digital Blocks
  336
- Architectural Description
  336
- Input Multiplexers
  337
- Input Clock Resynchronization
  337
- Input Data Synchronization
  338
- Timer Function
  338
- Output Demultiplexers
  338
- Block Chaining Signals
  338
- Clock Resynchronization Summary
  338
- Usability Exceptions
  339
- Block Interrupt
  339
- Counter Function
  339
- Counter Timing
  339
- Dead Band Function
  340
- Usability Exceptions
  340
- Block Interrupt
  340
- Usability Exceptions
  341
- Block Interrupt
  341
- PWMDBL Function
  341
- Usability Exceptions
  342
- Block Interrupt
  342
- CRCPRS Function
  342
- Usability Exceptions
  343
- Block Interrupt
  343
- SPI Protocol Function
  344
- SPI Protocol Signal Definitions
  344
- SPI Master Function
  345
- Usability Exceptions
  345
- Block Interrupt
  345
- SPI Slave Function
  345
- Asynchronous Transmitter Function
  346
- Asynchronous Transmitter and Receiver Functions
  346
- Block Interrupt
  346
- Usability Exceptions
  346
- Usability Exceptions
  347
- Block Interrupt
  347
- Asynchronous Receiver Function
  347
- DSM Function
  347
- Usability Exception
  348
- Block Interrupt
  348
- Register Definitions
  349
- Dxcxxdrx Registers
  350
- Timer Register Definitions
  350
- Counter Register Definitions
  351
- Dead Band Register Definitions
  351
- PWMDBL Register Definitions
  352
- CRCPRS Register Definitions
  352
- SPI Master Register Definitions
  353
- SPI Slave Register Definitions
  353
- Transmitter Register Definitions
  353
- Dxcxxcr0 Register
  354
- DSM Register Definitions
  354
- Receiver Register Definitions
  354
- Dxcxxcr1 Register
  358
- INT_MSK1 Register
  360
- Dxcxxfn Registers
  361
- Dxcxxin Registers
  362
- Dxcxxou Registers
  362
- Timing Diagrams
  364
- Timer Timing
  364
- Counter Timing
  367
- Dead Band Timing
  368
- Changing the PWM Duty Cycle
  368
- Kill Operation
  369
- PWMDBL Timing
  370
- CRCPRS Timing
  371
- SPI Mode Timing
  371
- SPIM Timing
  372
- SPIS Timing
  375
- Transmitter Timing
  378
- Receiver Timing
  380
- DSM Timing
  383
- Section E: Analog System
  384
- Top Level Analog Architecture
  384
- Interpreting the Analog Documentation
  388
- Application Description
  388
- Defining the Analog Blocks
  388
- Analog Functionality
  389
- Analog Register Summary
  390
- Architectural Description
  394
- Analog Interface
  394
- Analog Data Bus Interface
  395
- Analog Comparator Bus Interface
  395
- Analog Column Clock Generation
  395
- Column Clock Synchronization
  396
- Decimator and Incremental ADC Interface
  396
- Decimator
  396
- Incremental ADC
  396
- SAR Hardware Acceleration
  397
- Architectural Description
  397
- Analog Modulator Interface (Mod Bits)
  397
- Application Description
  397
- Analog Synchronization Interface (Stalling)
  397
- Application Description
  398
- SAR Timing
  400
- Register Definitions
  401
- CLK_CR3 Register
  401
- CMP_CR0 Register
  402
- ASY_CR Register
  403
- CMP_CR1 Register
  404
- DEC_CR0 Register
  404
- DEC_CR1 Register
  405
- CLK_CR0 Register
  405
- CLK_CR1 Register
  406
- AMD_CR0 Register
  406
- CMP_GO_EN Register
  407
- CMP_GO_EN1 Register
  407
- ALT_CR1 Register
  408
- ALT_CR0 Register
  408
- AMD_CR1 Register
  408
- CLK_CR2 Register
  409
- Analog Array
  410
- Architectural Description
  410
- Nmux Connections
  411
- Pmux Connections
  412
- Rbotmux Connections
  413
- Amux Connections
  414
- Cmux Connections
  415
- Bmux SC/SD Connections
  416
- Analog Comparator Bus
  417
- Temperature Sensing Capability
  417
- Analog Input Configuration
  418
- Architectural Description
  418
- Six Column Analog Input Configuration
  419
- Register Definitions
  420
- AMX_IN Register
  420
- AMUX_CFG1 Register
  421
- ABF_CR0 Register
  421
- Analog Reference
  422
- Architectural Description
  422
- Register Definitions
  423
- ARF_CR Register
  423
- Continuous Time Psoc ® Block
  426
- Architectural Description
  426
- Register Definitions
  427
- Accxxcr3 Register
  428
- Accxxcr1 Register
  430
- Accxxcr0 Register
  430
- Accxxcr2 Register
  431
- Switched Capacitor Psoc ® Block
  432
- Architectural Description
  432
- Application Description
  434
- Register Definitions
  435
- Ascxxcr0 Register
  436
- Ascxxcr1 Register
  437
- Ascxxcr2 Register
  437
- Ascxxcr3 Register
  438
- Asdxxcr0 Register
  439
- Asdxxcr1 Register
  440
- Asdxxcr2 Register
  440
- Asdxxcr3 Register
  441
- Two Column Limited Analog System
  442
- Architectural Description
  442
- Analog Interface
  442
- Analog Comparator Bus Interface
  443
- Analog Column Clock Generation
  443
- Single Slope ADC
  443
- Sample and Hold Feature
  445
- PWM ADC Interface
  445
- Analog Modulator Interface (Mod Bits)
  445
- Analog Array
  446
- Nmux Connections
  446
- Pmux Connections
  447
- Temperature Sensing Capability
  447
- Analog Input Configuration
  447
- Application Description for the SC Block
  451
- Psoc Device Distinctions
  451
- Analog Reference
  451
- Switched Capacitor Psoc Block
  451
- Continuous Time Psoc Block
  451
Register Definitions

453
- Summary Table for Two Column Limited Analog System Registers
  453
- 0,E6H DEC_CR0
  454
- 0,E7H DEC_CR1
  454
- DEC_CR0 Register
  454
- DEC_CR1 Register
  454
- 1,73H ACE_AMD_CR0
  455
- 1,E5H ADC0_TR
  455
- 1,E6H ADC1_TR
  455
- ACE_AMD_CR0 Register
  455
- Ace_Amx_In
  455
- ACE_AMX_IN Register
  455
- Adcx_Tr Register
  455
- 1,76H ACE_CMP_CR0
  456
- 1,77H ACE_CMP_CR1
  456
- ACE_CMP_CR0 Register
  456
- ACE_CMP_CR1 Register
  456
- Ace_Cmp_Gi_En
  456
- ACE_CMP_GI_EN Register
  456
- Gio5
  456
- 1,7Ah ACE_ALT_CR0
  457
- 1,7Bh ACE_ABF_CR0
  457
- 1,7Dh ACE00CR1
  457
- ACE_ALT_CR0 Register
  457
- 1,7Eh ACE00CR2
  458
- 1,7Fh ASE10CR0 Fval
  458
- 1,83H ACE_AMD_CR1
  458
- 1,86H ACE_ADC0_CR
  459
- 1,87H ACE_ADC1_CR
  459
- Ace_Pwm_Cr
  459
- Ace_Clk_Cr0
  460
- Ace_Clk_Cr1
  460
- Ace_Clk_Cr3
  460

Cypress CY8C28 series Manual (211 pages)

PSoC Development Kit

Brand: Cypress | Category: Microcontrollers | Size: 10 MB

Table of Contents
3
1 Introduction

7
- Installation
  8
  - Installing Psoc 5 Development Software
    9
- Psoc Development Board
  10
- Kit Revision
  12
- Additional Resources
  13
- Document Revision History
  14
2 Loading My First Psoc Project

15
3 Sample Projects

33
- ADC to LCD Project
  41
- ADC to UART with DAC
  48
- Capsense
  60
- CY8C29 Family Processor Module Code Examples
  70
  - ADC to LCD Project
    78
  - ADC to LCD with DAC and UART
    85
- CY8C38 / CY8C55 Family Processor Module Code Examples
  102
  - ADC to LCD Project
    111
  - ADC to UART with DAC
    118
  - Usb Hid
    135
  - Capsense
    149
  - SAR ADC (Psoc 5 Only)
    158
Appendix A. Board Specifications and Layout

175
- A.1.2 Power Supply Configuration Examples
  176
- A.1.3 Prototyping Components
  181
- A.1.4 LCD Module
  183
- A.1.5 Capsense Elements
  184
- A.1.7 Expansion Ports
  188
- A.2 Schematics
  191
- A.2.2 CY8C28 Family Processor Module
  192
- A.2.3 CY8C29 Family Processor Module
  193
- A.2.4 CY8C38 Family Processor Module
  194
- A.2.5 CY8C55 Family Processor Module
  195
- A.2.6 Enabling Boost Component in Psoc 3 and Psoc 5 Processor Modules
  196
- A.3.2 CY8C28 Family Processor Module
  198
- A.3.4 CY8C38 Family Processor Module
  199
- A.3.5 CY8C55 Family Processor Module
  200
Appendix B. Miniprog3

203
- B.4 Protection Circuitry
  204
Appendix C. Miniprog3 Technical Description

205
- C.1 Interfaces
  206
- C.2 Connectors
  207
- C.3 Power
  209

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Cypress CY8C28 series Manuals

Cypress CY8C28 series Technical Reference Manual (571 pages)

Table of Contents

Contents Overview

Register Definitions

Cypress CY8C28 series Manual (211 pages)

Table of Contents

1 Introduction

2 Loading My First Psoc Project

3 Sample Projects

Appendix A. Board Specifications and Layout

Appendix B. Miniprog3

Appendix C. Miniprog3 Technical Description

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