Spectrum Digital, Inc
2.3 LEDs
This section describes the LEDs on the TMS320C5517 EVM.
2.4 Jumpers
WARNING : Jumpers should NOT be moved/changed with the power on !
The figure below shows the jumper positions on the TMS320C5517 EVM.
Figure 2-2, TMS320C5517 EVM Jumpers
D1
L1
C3
RN3
1
L2
R4
R6
R5
J 3
C17
EM U USB
A1
C18
C21
C23
L3
U14
C29
C33
J8
U25
1
2
U17
C40
C46
TP11
C47
Q 4
L5
+
TP44
TP18
GND
J 13
GND
TP19
VBUS
1
USB3. 3
TM S320C5517 EVM
ASSY 514660 REV
J 16
SD0
U60
I R I N
TP29
U59
GND
R80
R81
C89
I R OUT
U61
Q7
R89
R92
1
P3
2-8
Table 14: TMS320C5517 LEDs
Schematic
LED #
Page
DS1
N/A
DS2
34
DS3
34
DS4
34
DS5
2
DS6
21
IRD1
36
Infrared
U60
36
JP4
JP45
1
J31
1
JP45
U3
TP1
1
2
U1
GND
J 24
J2
1
U7
TP51
JP4
U9
1
2
GND
1
C4
J 26
R232
C5
U15
R8
C22
L4
C25
C28
1
2
R11
U23
C32
+
R162
R16
+
C338
J 25
+
R169
C342
C337
C44
U29
R24 R25
Q3
U27
JP62
U31
R520
C52
C53
U32
C341
R39
R41
TP13
U33
U34
U35
SW 3
ON
C339
U37
TP47
GND
SW 4
O N
R42
R45
HPI _ON
U41
SEL_M M C0_I 2S
SEL1_M M C1_M CSPI
SEL0_M M C1_M CSPI
U83
DS4
DS3
DS2
U44
C356
R53
R425
R424
R423
U45
R54
U82
C354
U48
U49
U50
U52
C81
Y4
C84
U54
R70
J17
C80
2
1
Y3
S/ N
R75
U81
C86
R78
SW 11
ON
SW 12
ON
Q6
M SP430_SW OPT0
M SP430_SW OPT1
M SP430_SW OPT2
M SP430_SW OPT3
M SP430_SPI _OEN
M SP430
M SP430_SPI _DI R
RESET
M SP430 OPT
C90
R90
R91
J P52
M SP430 UART
C91
C92
R93
R95
U62
TP52
C93
GND
J19
M SP430 USB
JP52
Color
Signal
Green
Emulation Data Transfer Active
?
MSP430_PIN78
?
MSP430_PIN45
?
MSP430_PIN41
?
C5517 XF Bit, U24, Pin M8
Red
+5 Volts
IR_OUT
NA
IR Receiver
JP10
JP2
JP12
P1
P2
JP1
2
1
2
U4
1
1
U2
R1
U5
A1
A1
U10
TP4
G ND
TP56
U12
RN2
U8
2
R518
RN6
RN5
U21
1
RN8
RN7
U13
U16
2
R9
U24
P1
A1
1
1
R10
U71
R13
C24
R12
C35
JP12
R15
R17
TP8
U70
Y1
I NT0
R19
TP9
U20
TP48
RTC_CLKOUT
R21
C43
U68
U69
R23
GND
R26
P14
R28
A14
JP18
R29
U76
R30
1
R36
JP21
C54
VDD_I O2
VDD_I O1
1
JP22
JP23
U38
U39
Y2
VDDA_PLL
1
1
J10
R44
R43
1
BOOTM ODE0
TP15
U77
BOOTM ODE1
R46
R47
BOOTM ODE2
1
R48
BOOTM ODE3
JP25
2
BOOTM ODE4
R49
3V3_USB
EVM _1. 3
R50
BOOTM ODE5
SW 5
ON
U40
NOT USED
JP27
1
BOOTM PULSE
EN LDO_1V3/ I O1
TP16
R51
SOURCE
EN VCC_3V3
EN VCC_1V8
1
1
EN CPU_CORE
JP28
1
EVM VI N
1
U42
J P46
U43
GND
1
SW 6
ON
L6
TP24
C69
CPU_VCC_CORE_0
R57
C70
CPU_VCC_CORE_1
U46
R58
R59
TP25
LDO_1V3 ( DEFLDO1)
C71
VDD_I O1 ( DEFLDO2)
R60
TP26
R61
U47
2
1
VI N SEL
R66
U51
J14
EXT
TP27
JP61
J P31
BAT
L7
L8
1- 2 BAT
GND
TP28
J P32
2- 3 5V
C76
EVM 3. 3
1
U53
JP33
U55
U58
1
EVM VCORE
R69
L10
R73
R72
R74
1
R71
JP47
M SP430_PW R_EN
C79
R76
R77
D5
C82
C83
+
1
C85
R79
JP34
M ENU
UP
M ODE
SEL/
=
SHI FT
RW D
FW D
R109
TP53
GND
STOP
DN
REC
JP31
JP34
JP47
TMS320C5517 EVM Technical Reference
JP3
JP7
JP6
JP11
RESET
W AKEUP
TP3
TP42
SW 1
TP2
SW 2
W AKEUP
GND
M 1
DS5
XF
P8
J1
C2
U6
Q1
C6
JP7
CLKOUT
AI C
SDA
J5
Q2
TP45
TP5
JP56 JP55
XF
1
1
GND
1
1
JP11
SCL
U19
C27
TP6
P5
J6
TP7
I NT1
GND
FB1
C322
R14
SCL
C34
R18
U74
P4
I OVDD
VDI O4
1
JP17
JP16
TP12
J P53
R522
1
GND
FB4
1
1
U80
JP54
R516
M 2
U73
JP24
P9
1
C313
U79
LDO_EN
J15
1
TP49
GND
C312
J11
JP60
J P59
CLKI N
1
1
TP21
JP51 JP48
VPW R_I N
P7
C294
TP40
U72
FB16
C334
C306
P6
TP23
R64
R65
2
U75
GND
JP57
JP58
TP41
J 7
JP49
1
1
1
L9
GND
SW 7
2
4
2
4
2
4
2
4
C78
U78
1
3
1
3
1
3
1
3
D6
F1
TP46
GND
C87
J18
R82
TP31
+
M ax I nput : 5VDC, 4A.
B
Us e onl y r ec om m ended
power s uppl i es .
TP32
TP30
-
B
TP43
DS6
GND
J27 J28 J29
JP56
JP55
JP15
JP54
JP53
JP24
JP59
JP60
JP50
JP58
JP57
J30
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