Function Security Of The Vipa Cpus - VIPA System 100V Series Manual

Manual VIPA System 100V

Function security of the VIPA CPUs

Security
mechanisms
Event concerns
RUN → STOP
general
central digital outputs
central analog outputs
decentral outputs
decentral inputs
STOP → RUN
general
res. Power on
central analog outputs
decentral inputs
RUN general
PII: = Process image inputs
PIQ: = Process image outputs
HB100E - CPU - Rev. 12/12
Chapter 2 Hardware description Micro-PLC CPU 11x
The CPUs include security mechanisms like a watchdog (100ms) and a
parameterizable cycle time surveillance (parameterizable min. 1ms) that
stop res. execute a RESET at the CPU in case of an error and set it into a
defined STOP state.
The VIPA CPUs are developed function secure and have the following
system properties:
Effect
BASP (Befehls-Ausgabe-Sperre,
output lock) is set.
The outputs are set to 0V.
The voltage supply for the output channels is
switched off.
The outputs are set to 0V.
The inputs are read constantly from the slave and
the recent values are put at disposal.
First the PII is deleted, the call of the OB100
follows. After the execution of the OB, the BASP is
set back and the cycle starts with:
Delete PIQ → Read PII → OB1.
The behavior of the outputs at restart can be
preset.
The inputs are read constantly from the slave and
the recent values are put at disposal.
The program execution happens cyclically and can
therefore be foreseen:
Read PII → OB1 → Write PIQ.
i.e. command
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