Main (Video (4/4)) Schematic Diagram - Panasonic SDR-H80P Service Manual

SDR-H80P

8.16. MAIN (VIDEO (4/4)) SCHEMATIC DIAGRAM

H
11
DIGITAL
SIGNAL
PROCESS
12
AA20 AA17 Y19 W19 V19 Y20 W20 V20 P13 AB19 AA19 AB20 AB18 AA18 R18 N18 M18 L18 P17 N17 M17 L17 P16
13
14
15
16
17
18
TP3039
19
20
21 R3042
47k
22
23
24
25
26
27
28
11 12
I
IC3001
MN2WS0056SP1
(VIDEO/AUDIO/PROCESSOR)
LYCIO[7]
LYCIO[6]
LYCIO[5]
LYCIO[4]
LYCIO[3]
LYCIO[2]
LYCIO[1]
LYCIO[0]
CLK27C
AUDIO DIGITAL
DISC CONTROL/ZOOM CONTROL/
DOLRCK
SIGNAL PROCESS
EFECT CONTROL/JPEG/GUI
IPPBOOT
SCANEN
TESTSEL
MODE[2]
MODE[1]
MODE[0]
TMONOUT2
TMONOUT1
D/A D/A
TMONOUT0
CONVERTER CONVERTER
TMEMCLK
TAMMPCLK
CLKSEL[2]
CLKSEL[1]
CLKSEL[0]
N16 M16 P19 P18 R17 R16 R19 J19 J18 K18 G19 H19 P20 T19 U18 T18 R20 U19 U20 K19 R22 L22 L21 M22 N21 M21 N22 P22 P21 G22 G21 H22 J22 J21 E21 H21 J20 H20 K22 K21 L20 M20 N20 M19 N19 K20 R21 L19 T20 E19 M13 M12 N12
R3055
18K
0.5%
13 14
: VIDEO MAIN SIGNAL PATH IN REC MODE
: VIDEO MAIN SIGNAL PATH IN PLAYBACK MODE
J K L
0
VSS A19
0
YCIN[7]
A17
0
YCIN[6]
A18
0
YCIN[5] B18
0
YCIN[4] C18
0
YCIN[3]
D18
0
YCIN[2]
B19
0
YCIN[1] C19
0
YCIN[0] D19
0
CLK27X
C20
1.8 LYCIO[0-7]
VDDIO5
C22
0.4 LYCIO7
J16
0.9 LYCIO6
K16
0 LYCIO5
J17
1.2 LYCIO4
K17
0.6 LYCIO3
G17
0.7 LYCIO2
H17
0.7 TP3030 LYCIO1
G18
0.7 LYCIO0
H18
0.9
D21
1.8
R3140
VDDIO5 C21
33
AIDAT2
G20 TP3032
0 (0.6)
AIDAT1
F20
C3044 TP3033
0.5
DODAT F18
0.1u[KB] TP3034
1.0
E20
0.9 TP3035
DOBCK
F22
0.6 TP3036
DOMCK
F21
1.8
VDDIO5 D22
CLK27B E22
0.9
CLK27A
D20
CLK135
F19
0
VSSIO5 E18
0
H16
0
ILATCH
J15
0
L16
0
K15
0
K14
0
L14
0
L15
0
N15
0
P15
0
P14
0
R12
0
R14
0
M14
0
N14
0
M15
0
AVSS4 U22
3.0
AVDD4 T22
0
AVSS3
U21
3.0
AVDD3
T21
0
AVSS2 W21
3.0
AVDD2 V21
0 C3042
AVSS1
W22
3.0 0.1u[KB]
AVDD1
V22
0
AVSS0 Y21
3.0
AVDD0 Y22
NC C3041
B22
NC
B21
0.01u[KB]
NC A22
NC A21
C3040
10u 6.3V
NOTE:
DO NOT USE ANY PART NUMBER SHOWN ON
THIS SCHEMATIC DIAGRAM FOR ORDERING.
WHEN YOU ORDER A PART, PLEASE REFER
TO PARTS LIST.
NOTE:
CIRCUIT VOLTAGE AND WAVEFORM DESCRIBED
HEREIN SHALL BE REGARDED AS REFERENCE
INFORMATION WHEN PROBING DEFECT POINT,
BECAUSE IT MAY DIFFER FROM AN ACTUAL MEASURING
VALUE DUE TO DIFFERENCE OF MEASURING
INSTRUMENT AND ITS MEASURING CONDITION
AND PRODUCT ITSELF.
NOTE:
THE MEASUREMENT MODE OF THE DC VOLTAGE ON THIS DIAGRAM IS PLAYBACK MODE.
THE MEASUREMENT MODE OF THE DC VOLTAGE IN THE BRACKETS ( ) ON THIS DIAGRAM
IS RECORD MODE. (SP MODE)
15 16 17
46
: AUDIO MAIN SIGNAL PATH IN REC MODE
: AUDIO MAIN SIGNAL PATH IN PLAYBACK MODE
TO
MAIN (VIDEO (2/4))
SECTION
TO MAIN CN (J-7)
<TO LCD>
LYCIO0
LYCIO0 (J68)
LYCIO1
LYCIO1 (J69)
LYCIO2
LYCIO2 (J70)
LYCIO3
LYCIO3 (J71)
LYCIO4
LYCIO4 (J72)
LYCIO5
LYCIO5 (J73)
LYCIO6
LYCIO6 (J74)
LYCIO7
LYCIO7 (J75)
CLK27C (J76)
TO MAIN CN (K-7)
<TO AVIO>
SDO0 (J60)
SDI (J61)
LRCK (J62)
BCK (J63)
MCK (J64)
VIDEO_ADJ (J65)
UNI_COUT (J66)
UNI_YOUT (J67)
TO MAIN CN (E-7)
<TO LENS DRIVE>
CLK27M (J36)
TO MAIN CN (E-7)
<TO POWER>
POW_VREF (J113)
TO MAIN CN (F-7)
<TO SYSCON>
UPDATE (J104)
LOCATION MAP
ARM_HDD_OFF_L (J109)
1/4 2/4
3/4 4/4
SDR-H80, H81, H90
MAIN (VIDEO (4/4))
SCHEMATIC DIAGRAM
18 19 20