Main (Video (2/4)) Schematic Diagram - Panasonic SDR-H80P Service Manual

SDR-H80P

8.14. MAIN (VIDEO (2/4)) SCHEMATIC DIAGRAM

TP3038 TP3011
1
2
3
4
5
6
7
8 G2 F6 F5 F4 F3 F2 F1 E5 E4 E3 E2 E1 F7 E7 E6 G1 D4 D3 D2 C2 C3 D5 B13 B12 A10 L9 K9 E10 D10 B11 C10 B10 G8 G9 H9 A11 A13 J9 F10 G10 H10 J10 C8 D8 D7 MM B7 C9 A9 A7 D9 F8 E8
9
10
H
11 12
: VIDEO MAIN SIGNAL PATH IN REC MODE
: VIDEO MAIN SIGNAL PATH IN PLAYBACK MODE
R3194
47k
1.8
0
C3081
100p
0
Q3009
UNR32A300L
(SWITCHING)
R3164 82
R3162 33
R3161 33
R3160 33
R3159 33
L3007 L3006
R3006 10uH 10uH
2.0x1.25 2.0x1.25
1.5k 0.5%
C3056
0.01u[KB]
R3001
39[D] C3053 C3051
0.01u[KB]
4.7u[KB]
F9 E9 C4 C1 A8 B8 C7 D6 C6 C5 B3 B5 B6 A6 B4 A5 A4 A3 B2 B1 A2 A1
TESTCK4
TESTCK3
TESTCK2
TESTCK1
TESTCK0
SD USB
VDDIO4
INTERFACE INTERFACE
ATATX
ATAINTRQ
ATAIORDY
XATARESET
XATADMACK
VDDIO4
ATADMARQ
XATAWR
XATARD
XATACS3
XATACS1
VSSIO4
ATADA[2]
ATADA[1]
ATADA[0]
VSSIO4
ATADD[15]
ATADD[14]
ATADD[13]
ATADD[12]
ATAPI ATADD[11]
INTERFACE
ATADD[10]
ATADD[9]
ATADD[8]
VDDIO4
ATADD[7]
ATADD[6]
ATADD[5]
ATADD[4]
ATADD[3]
ATADD[2]
ATADD[1]
ATADD[0]
VSSIO4
CLK45M_ZB
SVD_ZA
LINPWM
VSSIO4
OSDBLKB
OSDBLKA
OSDVD
IC3001 OSDHD
MN2WS0056SP1 VDDIO4
(VIDEO/AUDIO/PROCESSOR) OSDVB
OSDVG
OSDVR
OSDCLK
VDDIO4
VDD
LCDPOL
LCDVBLK
LCDHD
I
13 14
: AUDIO MAIN SIGNAL PATH IN REC MODE
: AUDIO MAIN SIGNAL PATH IN PLAYBACK MODE
R3163 33
NC
L12
NC K13
L13
L10
R3086
N10
4700
K12
N13
3.3
R3087
A14
0 10k
R3129
E15
0 100k R3128 82
E14
3.1
R3127 82
F14
3.1 C3049 R3126 33
A12
3.1 0.01u[KB] R3125 22
C13
3.3 R3085
5600
B14
3.0 (0.1)
R3124 82
J12
3.0 R3123 22
J11
3.0 R3122 22
H11
0 R3121 33
C11
3.0 R3120 33
C12
0
D11
3.0 R3119 33
E11
3.0 R3118 33
F11
0.7
R3117 33
G11
0
E12
0.6
D12
0.6
F12
0.6
D13
0.6
E13
0.6
F13
0.6
G12
0.6
H12
0.6
G13
3.3
R3084
C14
1.2
10k
H13
1.2
J13
1.0
G14
1.0
H14
1.0
J14
1.0
F15
1.0
G15
1.0
H15
0
F17
C15
D15
D14
0
G16
E16
F16
C16
D16
3.3
B20
C17
D17 C3047
E17 0.1u[KB]
A16
3.3
A20
1.2
A15
B15 C3046
0.01u[KB]
B16
B17 C3045
0.1u[KB]
NOTE:
CIRCUIT VOLTAGE AND WAVEFORM DESCRIBED
HEREIN SHALL BE REGARDED AS REFERENCE
INFORMATION WHEN PROBING DEFECT POINT,
BECAUSE IT MAY DIFFER FROM AN ACTUAL MEASURING
VALUE DUE TO DIFFERENCE OF MEASURING
INSTRUMENT AND ITS MEASURING CONDITION
J K L AND PRODUCT ITSELF.
NOTE:
THE MEASUREMENT MODE OF THE DC VOLTAGE ON THIS DIAGRAM IS PLAYBACK MODE.
THE MEASUREMENT MODE OF THE DC VOLTAGE IN THE BRACKETS ( ) ON THIS DIAGRAM
IS RECORD MODE. (SP MODE)
15 16 17
44
LOCATION MAP
1/4
TO MAIN CN (J-7)
<TO LCD>
LCD_SCK (J77)
LCD_SD (J78)
3/4
LCD_CS (J79)
TO MAIN CN (L-7) <TO USB HOST>
USB_HOST_INT (J51)
USB_VBUS_CURDE_L (J50)
TO MAIN CN (M-6)
<TO SYSCON/HDD>
HDD_UNLOAD (J15)
TO MAIN CN (F-7)
<TO SYSCON>
HOST_REQ (J107)
ARM_REQ (J108)
TO MAIN CN (M-7)
<TO SD CARD>
CARD_PRO (J38)
CARD_DET (J39)
SD_CLK (J40)
CMD_O (J41)
SDDATA3 (J42)
SDDATA2 (J43)
SDDATA1 (J44)
SDDATA0 (J45)
TO MAIN CN (D-7)
<TO RESIZE>
12MCLK (J124)
TO MAIN CN (M-7)
<TO USB HOST>
UNI_USB_D- (J46)
UNI_USB_D+ (J47)
TO MAIN CN (L-7/M-7)
<TO USB HOST/HDD>
XATAINTRQ (J5)
XATAIORDY (J4)
XATARESET (J2)
XATADMACK (J11)
XATADMARQ (J13)
XATAWR (J3)
XATARD (J12)
XATACS3 (J9)
XATACS1 (J8)
ATADA2 (J10)
ATADA1 (J6)
ATADA0 (J7)
TO MAIN CN (L-6)
<TO HDD>
ATADD[0-15] (J14)
R3104
120 ATADD15
ATADD14
ATADD13
ATADD12
R3103
ATADD11 TO MAIN CN (M-7)
120
ATADD10 <TO USB HOST>
ATADAT[0-15] (J1)
ATADD9
ATADD8
R3102
ATADD7
120
ATADD6
ATADD5
ATADD4
ATADD3
ATADD2
ATADD1
ATADD0
R3101
120
ATADAT[0-15]
ATADAT0
ATADAT1
ATADAT2
ATADAT3
ATADAT4
ATADAT5
ATADAT6
ATADAT7
ATADAT8
ATADAT9
ATADAT10
ATADAT11
ATADAT12
ATADAT13
ATADAT14
ATADAT15
NOTE:
DO NOT USE ANY PART NUMBER SHOWN ON
THIS SCHEMATIC DIAGRAM FOR ORDERING.
WHEN YOU ORDER A PART, PLEASE REFER
TO PARTS LIST.
SDR-H80, H81, H90
MAIN (VIDEO (2/4))
SCHEMATIC DIAGRAM
18 19
2/4
4/4
TO
MAIN (VIDEO (4/4))
SECTION
20