Main (Tg/Afe) Schematic Diagram - Panasonic SDR-H80P Service Manual

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SDR-H80P
8.6.

MAIN (TG/AFE) SCHEMATIC DIAGRAM

(MAIN P.C.B.)
REFER TO MAIN CONNECTION
G
TO MAIN CN (H-5)
<TO SYSCON>
(G23) CG_RST
TO MAIN CN (I-5)
<TO RESIZE/ KAO>
(G21) TG_VD
(G22) TG_HD
F
TO MAIN CN (I-5)
<TO RESIZE/ KAO>
(G19) ADIN_RESIZE9
(G19) ADIN_RESIZE8
(G19) ADIN_RESIZE7
E
(G19) ADIN_RESIZE6
(G19) ADIN_RESIZE5
(G19) ADIN_RESIZE4
(G19) ADIN_RESIZE3
(G19) ADIN_RESIZE2
(G19) ADIN_RESIZE1
(G19) ADIN_RESIZE0
TO MAIN CN (I-4)
D
<TO CCD>
(G8) V1
(G9) V2
(G10) V3
(G11) V4
(G12) V5
(G13) V6
C
NOTE:
DO NOT USE ANY PART NUMBER SHOWN ON
THIS SCHEMATIC DIAGRAM FOR ORDERING.
WHEN YOU ORDER A PART, PLEASE REFER
TO PARTS LIST.
NOTE:
THE MEASUREMENT MODE OF THE DC VOLTAGE ON
THIS DIAGRAM IS STOP MODE.
NOTE:
CIRCUIT VOLTAGE AND WAVEFORM DESCRIBED
HEREIN SHALL BE REGARDED AS REFERENCE
INFORMATION WHEN PROBING DEFECT POINT,
B
BECAUSE IT MAY DIFFER FROM AN ACTUAL MEASURING
VALUE DUE TO DIFFERENCE OF MEASURING
INSTRUMENT AND ITS MEASURING CONDITION
AND PRODUCT ITSELF.
TO MAIN CN (G-4)
<TO POWER>
(G15) AF_5V
A
1
2
12.0
C6 VH
-
C7 D9
-
C8 V3
-
C9 V2
-
TP316
C10 D8
3.3
D1 DVDD4
D2 HL
C303
0.1u[KB]
0
10V
D3 DVSS4
0
D4 VM
-
D8 D4
-
D9 D6
3.0
D10 DVDD2
0
E1 DVSS4
0
C304
E2 DVSS4
0.1u[KB]
0
10V
E3 DVSS4
-
E8 V4
-
E9 D5
1.0
E10 D2
C306
0.1u[KB]
10V
3.3
5
4
IC301
VOUT
NC
C0DBGFC00031
(+3.3V REGULATOR)
VDD
GND
CE
1
2
3
4.8
0
4.8
C302
1u[KB]
10V
C301
0.1u[KB]
10V
3
4
: VIDEO MAIN SIGNAL PATH
C310
0.1u[KB]
10V
R323
C315
C331
C305
0
0.1u[KB]
5p
0.1u[KB]
10V
TP317
TP318
C312
22p
C5
C4
C3
C2
C1
B10
B9
B8
B7
B6
B5
B4
B3
B2
B1
A10
A9
A8
A7
A6
A5
A4
A3
IC302
C1AB00003001
(CAMERA SIGNAL PROCESS/
TIMING GENERATOR/ CCD V-DRIVE)
F1
F2
F3
F8
F9
F10
G1
G2
G3
G8
G9
G10
H1
H2
H3
H4
H5
H6
H7
H8
H9
H10
J1
R316
33k
TP304
C311
0.01u[KB]
16V
C307
R321
0.1u[KB]
0
10V
C314
R317
10u
100k
10V
5
6
7
36
L304
10u
D302
MA2S111008
C318
0.1u[KB]
10V
C319
22p
C326
1000p[KB]
C327
0.1u[KB]
A2
A1
16V
C324
4.7u
TP308
12.0
16V
K10
VHH
2.9
CS
K9
3.0
K8
AVDD2
C321 0.1u[KB]
1.0
VRB
K7
2.0
VRT
K6
C332
0
C323 0.1u[KB]
0.1u[KB]
AVSS12
K5
1.8
CCDIN
K4
C322
C328
2.0
0.1u[KB]
K3
0.1u[KB]
FBC
10V
2.0
SHC
K2
0
K1
CCDGND
2.9
SDI
J10
ID
J9
TP301
-
ADCK
J8
0
NC
J7
2.9
J6
SCK
0
AVSS12
J5
0
J4
AVSS12
J2
J3
TP306
R318
47
C320
TP307
C325
1000p[KB]
10u
10V
L302
L301
10u
0
L303
10uH
D301
MA2S728008
SDR-H80, H81, H90
MAIN (TG/ AFE) SCHEMATIC DIAGRAM
8
9
TO MAIN CN (G-4)
<TO POWER>
CAM_12V (G17)
TO MAIN CN (I-4)
<TO CCD>
CCD_12V (G6)
TO MAIN CN (I-4)
<TO CCD>
CCD_RESET (G5)
H2 (G1)
H1 (G2)
SUB (G4)
TO MAIN CN (I-5)
<TO RESIZE/ KAO>
RESIZE_FCK (G20)
TO MAIN CN (I-4)
<TO CCD>
CCDOUT (G7)
TO MAIN CN (H-5)
<TO SYSCON>
CAM_CG_CS (G24)
CGAFE_DTO (G25)
CGAFE_CLK (G26)
TO MAIN CN (G-4)
<TO POWER>
REGD3V (G16)
CAM-7.5V (G18)
TO MAIN CN (I-4)
<TO CCD>
CCD_VL (G3)
TO MAIN CN (G-4)
<TO POWER>
D_GND (G14)
10

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