Main (Video (1/4)) Schematic Diagram - Panasonic SDR-H80P Service Manual

8.13. MAIN (VIDEO (1/4)) SCHEMATIC DIAGRAM

(MAIN P.C.B.)
REFER TO MAIN CONNECTION
TO MAIN CN (E-7)
R3134
<TO POWER>
0
(J114) REGD1.2V
N
L3001
J0JBC0000107
(J115) REGD1.8V
L3002
J0JBC0000107
(J116) REGD3V
AVDDPLL,AVDDTR
(J117) REGA3.3V
R3135
0
(J118) REGD3.3V
L3004 10u
DAC
PLL
(J119) A3V
L3005 10u
C3002
C3001
100u
6.3V
6.3V
10u
[X]
(J120) D_GND
M
TO MAIN CN (J-6/K6)
<TO MEMOY>
(J22) DRAMSDAT[0-31]
(J23) DRAMSDQM0
(J24) DRAMSDQM1
(J25) DRAMSDQM2
(J26) DRAMSDQM3
(J27) XDRAMSWE
(J28) XDRAMSCAS
(J29) XDRAMSRAS
(J30) DRAMSCLKO
(J31) DRAMSCKE0
(J32) DRAMSCS0
(J33) DRAMSBA0
(J34) DRAMSBA1
L (J35) DRAMSADR[0-12]
NOTE:
DO NOT USE ANY PART NUMBER SHOWN ON
THIS SCHEMATIC DIAGRAM FOR ORDERING.
WHEN YOU ORDER A PART, PLEASE REFER
TO PARTS LIST.
NOTE:
CIRCUIT VOLTAGE AND WAVEFORM DESCRIBED
HEREIN SHALL BE REGARDED AS REFERENCE
K INFORMATION WHEN PROBING DEFECT POINT,
BECAUSE IT MAY DIFFER FROM AN ACTUAL MEASURING
VALUE DUE TO DIFFERENCE OF MEASURING
INSTRUMENT AND ITS MEASURING CONDITION
AND PRODUCT ITSELF.
NOTE:
THE MEASUREMENT MODE OF THE DC VOLTAGE ON THIS DIAGRAM IS PLAYBACK MODE.
THE MEASUREMENT MODE OF THE DC VOLTAGE IN THE BRACKETS ( ) ON THIS DIAGRAM
IS RECORD MODE. (SP MODE)
TO MAIN CN (F-7)
<TO SYSCON>
(J102) NARMTRST
TO MAIN CN (I-7)
<TO MAIN CN>
(J80) ARMTDI
(J81) ARMTDO
J
(J82) ARMTCK
(J83) ARMTMS
(J84) TRACECLK
(J85) TRACESYNC
(J93) PIPESTA[0-2]
(J92) TRACEPKT[0-7]
(J86) EXTRGO0
(J87) RTCK
(J88) DBGR
(J89) DBGA
(J90) TXD
(J91) RXD
TO MAIN CN (E-7)
I
<TO SUB POWER>
(J121) LCD_ON_H
(J122) LCD_BL_ON_H
TO MAIN CN (F-7)
<TO SYSCON>
(J105) FRP
TO MAIN CN (G-7)
<TO SYSCON>
(J101) CAM_WAKEUP
H
1 2
: VIDEO MAIN SIGNAL PATH IN REC MODE
: VIDEO MAIN SIGNAL PATH IN PLAYBACK MODE
C3005
C3004 10u
C3003
4.7u[KB] 6.3V
4.7u[KB]
DRAMSDAT[0-31]
DRAMSADR[0-12]
DRAMSADR0
DRAMSADR1
DRAMSADR2
DRAMSADR3
DRAMSADR4
DRAMSADR5
DRAMSADR6
DRAMSADR7
DRAMSADR8
DRAMSADR9
DRAMSADR10
DRAMSADR11
DRAMSADR12
PIPESTA[0-2]
TRACEPKT[0-7]
PIPESTA0
PIPESTA1
PIPESTA2
TRACEPKT0
TRACEPKT1
TRACEPKT2
TRACEPKT3
TRACEPKT4
TRACEPKT5
TRACEPKT6
TRACEPKT7
R3029
R3030
100k 100k
Q3003
UNR31A100L
(SWITCHING)
3.0
1.0
3.0
R3179 10k
3.0
Q3004
0
UNR31A100
(SWITCHING)
3.0
R3180 10k
A
3 4 5
: AUDIO MAIN SIGNAL PATH IN REC MODE
: AUDIO MAIN SIGNAL PATH IN PLAYBACK MODE
L11 K11 K10 M5 L5 M6 M4 J3 J2 J1 M2 L6 N8 M8 H7 H6 L4 L2 R7 P8 P7 P6 P5 P4 P3 H8 L1 P2 P1 N7 N6 N5 N4 N3 N2 N1 H5 H4 H3 H2 H1 G7 G6 G5 G4 G3
C3011
0.1u[KB]
AA1 NC
NC
AA2
AB1 NC
AB2 NC
-
XDRAMSCS[0]
K1
-
M3 DRAMSBANK[0]
-
DRAMSBANK[1]
1.2 L3
VDD
M1
-
KB DRAMSADR[0]
-
DRAMSADR[1]
L7
-
DRAMSADR[2]
K7
-
K6 DRAMSADR[3]
0
VSS
L8
-
K5 DRAMSADR[4]
-
K4 DRAMSADR[5]
MEMORY
-
DRAMSADR[6]
K3 INTERFACE
-
K2 DRAMSADR[7]
0
VSS
M7
-
DRAMSADR[8]
J8
-
J7 DRAMSADR[9]
-
DRAMSADR[10]
J6
-
DRAMSADR[11]
J5
-
J4 DRAMSADR[12]
1.8
VDDIO5
R1
C3013 1.8
0.01u[KB]
R2 VDDIO5
0
U6 VSSIO5
-
TDI
AB3
R3022 1.8
AA4 TDO
-
TCK
AA3
10k -
TMS
W3
R3023 -
Y2 XTRST
10k
3.3
DBGEN
V4
3.3
VDDIO4
Y1
-
U1 TRACECLK
C3015 -
TRACESYNC
U2
0.01u[KB] -
R6 PIPESTA[0]
-
T6 PIPESTA[1]
-
PIPESTA[2]
U5
-
R5 TRACEPKT[0]
-
TRACEPKT[1]
T5
-
TRACEPKT[2]
U4
-
R4 TRACEPKT[3]
3.3
VDDIO4
T1
0
VSSIO4
V5
-
T4 TRACEPKT[4]
C3016 -
TRACEPKT[5]
U3
0.1u[KB] -
R3 TRACEPKT[6]
-
T3 TRACEPKT[7]
3.3
VDDIO4
T2
0
IC3001
W4 VSSIO4
-
MN2WS0056SP1
EXTRGO[0]
V2
(VIDEO/AUDIO/PROCESSOR)
EXTRGO[1]
V3
-
V1 RTCK
-
DBGR
W2
-
DBGA
W1
0
Y3 VSSIO4
1.0
SCK2
W5
2.8
AA5 SO2
2.8
Y5 SI2
0
SY
T7
3.0
Y4 ICR
3.0
PWM0
U7
0
PWM1
U8
R3184
100k
D
B C E F G
6 7
43
LOCATION MAP
1/4 2/4
1
3/4 4/4
2
3
4
5
6
7
8
9
10
TO
MAIN (VIDEO (3/4))
SECTION
SDR-H80, H81, H90
MAIN (VIDEO (1/4))
SCHEMATIC DIAGRAM
8 9 10
SDR-H80P