Aiwa XR-MSK3 Service Manual page 38

IC, LC74781M-9017
Pin No. Pin Name
1 VSS1
2 Xtal IN
3 Xtal OUT
4 CTRL1
5 BLANK
6 OSC IN
7 OSC OUT
8 CHARA
9 CS
10 SCLK
11 SIN
12 VDD2
13 CV OUT
14 NC
15 CV IN
16 VDD1
17 SYN IN
18 SEP C
19 SEP OUT
20 SEP IN
21 CTRL2
22 CTRL3
I/O
— GND connection terminal. (Digital ground terminal).
I
External X'tal and capacitor for internal sync generator, or the external clock are connected to
this terminal. (2fsc or 4fsc).
O
Either the external clock input mode or the X'tal generator mode is selected by this selector
I
terminal. L: X'tal generator mode, H: External clock input.
Blank signal (character and the green ORed signal) is output from this terminal.
O (MODE 0: composite sync signal is output at H.) When reset (RST terminal = L), the X'tal
clock signal is output. (It is not output when reset by the reset command).
I
External coil and capacitor for the character output dot clock generator are connected to this
O terminal.
The character signal is output from this terminal. (MOD 0: when H, the external sync signal
identification signal is output from this terminal. This output signal tells whether the external
O sync signal is present or not. When external sync signal is present, H is output.) When reset
(RST terminal = L), the dot clock signal (LC oscillator) is output.
(It is not output when reset by the reset command).
Enable signal for the serial data input is input to this terminal. The serial data input is enabled
I
at L. Pull-up resistor is built-in. (Hysteresis input).
Clock of the serial data input is input to this terminal. Pull-up resistor is built-in.
I
(Hysteresis input).
I Serial data input terminal. Pull-up resistor is built-in. (Hysteresis input).
— Power supply for the composite video signal level adjustment. (Analog power supply).
O Composite video signal output terminal.
— Connected to GND or not connected.
I Composite video signal input terminal.
— Power supply (+5V digital power supply).
Video signal for the internal sync separator circuit is input to this terminal. (When the internal
I sync separator circuit is not used, the horizontal sync signal or composite sync signal is input
to this terminal).
— Internal sync separator circuit bias voltage monitoring terminal.
The composite sync output signal of the internal sync separator circuit is output from this
O terminal. (H: MOD 1. H: during internal sync mode. L: during external sync mode.)
(When internal sync separator circuit is not used, the SYN IN input signal is output from
this terminal).
The output signal of the SEP OUT terminal is integrated so that the vertical sync signal is input
to this terminal. An integrator circuit must be connected between the SEP OUT terminal and
I
this terminal. When this terminal is not used, it must be connectedto VDD1.
When selecting any of the NTSC or PAL or PAL-M or PAL-N system, the pin setting has
priority. When L, the NTSC system is selected after resetting. Selection of either NTSC or PAL
I
or PAL-M or PAL-N system by the command becomes effective. H: PAL-M system.
Controls whether or not to input the VSYNC signal to the SEPIN input. L: to input the
I
VSYNC signal. H: not to input the VSYNC signal.
Description
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