Aiwa XR-MSK3 Service Manual page 36

Pin No. Pin Name
39 GTOP
40 XVCF
41 XPCLK
42 GFS
43 RFCK
44 C2PO
45 XROF
46 MNT3
47 MNT2
48 MNT1
49 MNT0
50 APTR
51 APTL
52 VSS
53 XTAI
54 XTAO
55 XTSL
56 FSTT
57 FSOF
58 C16M
59 MD2
60 DOUT
61 EMPH
62 WFCK
63 SCOR
64 SBSO
65 EXCK
66 SQSO
67 SQCK
68 D MUTE
69 SENS
70 XRST
71 DATA
72 XLAT
73 VDD
74 CLOK
75 SEIN
76 CNIN
I/O
O DA11 output when PSSL=1. GTOP output when PSSL=0.
O DA10 output when PSSL=1. XVCF output when PSSL=0.
O DA09 output when PSSL=1. XPLCK output when PSSL=0.
O DA08 output when PSSL=1. GFS output when PSSL=0.
O DA07 output when PSSL=1. RFCK output when PSSL=0.
O DA06 output when PSSL=1. C2PO output when PSSL=0.
O DA05 output when PSSL=1. XRAOF output when PSSL=0.
O DA04 output when PSSL=1. MNT3 output when PSSL=0.
O DA03 output when PSSL=1. MNT2 output when PSSL=0.
O DA02 output when PSSL=1. MNT1 output when PSSL=0.
O DA01 output when PSSL=1. MNT0 output when PSSL=0.
Aperture compensation control output.
O
This pin outputs a high signal when the right channel is used.
Aperture compensation control output.
O
This pin outputs a high signal when the left channel is used.
— GND.
I
Crystal oscillation circuit input.
O Crystal oscillation circuit output.
I Crystal selector input.
O 2/3 frequency divider output for Pins 53 and 54.
O 1/4 frequency divider output for Pins 53 and 54.
O 16.9344MHz output. (V16M output in CLV-W and CAV-W modes)
I Digital-out on/off control. High: on; low: off
O Digital-out output.
Outputs a high signal when the playback disc has emphasis, and a low signal when
O
there is no emphasis.
I WFCK (write frame clock) output.
O Outputs a high signal when either subcode sync S0 or S1 is detected.
O Sub P to W serial output.
I SBSO readout clock input.
O Sub Q 80-bit and PCM peak, level metter and internal status outputs.
I SQSO readout clock input.
I High: mute; low: release
— SENS output to CPU.
I System reset. Reset when low.
O Serial data input from CPU.
O Latch input from CPU. Serial data is latched at the falling edge.
—
Power supply (5V).
Serial data transfer clock input from CPU.
O
I SENS input from SSP.
Track jump count signal input.
I
Description
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