Fluke ScopeMeter 123 Service Manual page 52

123
Service Manual
The sample rate depends on the sample clock supplied to pin 24. The sample rate is 5
MHz or 25 MHz, depending on the instrument mode. The ADC input signal is sampled
on the rising edge of the sample clock. The digital equivalent of this sample is available
on the outputs D0-D7 with a delay of 6 sample clock cycles.
The reference voltages REFADCT and REFADCB determine the input voltage swing
that corresponds to an output data swing of 00000000 to 11111111 (D0-D7). The
reference voltages are supplied by the reference circuit on the Trigger part. The ADC
output voltages MIDADC-A/B are supplied to the C-ASIC's (input pin 28), and are
added to the conditioned input signal. The MIDADC voltage matches the middle of the
C-ASIC output swing to the middle of the ADC input swing.
Current IREF is supplied to pin 7 of the ADC's via R403/R453 for biasing internal ADC
circuits.
The D-ASIC can disable the ADC conversion by making the STBY-A/STBY-B line pin
1 high. Conversion also stops if the sample clock stops.
ADC data acquisition for traces and numerical readings
During an acquisition cycle, ADC samples are acquired to complete a trace on the LCD.
Numerical readings (METER readings) are derived from the trace. So in single shot
mode a new reading becomes available when a new trace is started.
The test tool software starts an acquisition cycle. The D-ASIC acquires data from the
ADC, and stores them internally in a cyclic Fast Acquisition Memory (FAM). The D-
ASIC also makes the HOLDOFF line low, to enable the T-ASIC to generate the trigger
signal TRIGDT. The acquisition cycle is stopped if the required number of samples is
acquired. From the FAM the ADC data are moved to the RAM D475. The ADC data
stored in the RAM are processed and represented as traces and readings.
Triggering (HOLDOFF, TRIGDT, Randomize)
To start a new trace, the D-ASIC makes the HOLDOFF signal low. Now the T-ASIC
can generate the trigger signal TRIGDT. For signal frequencies higher than the system
clock frequency, and in the random repetitive sampling mode, no fixed time relation
between the HOLDOFF signal and the system clock is allowed. The RANDOMIZE
circuit desynchronizes the HOLDOFF from the clock, by phase modulation with a LF
ramp signal.
Trigger qualifying (ALLTRIG, TRIGQUAL)
The ALLTRIG signal supplied by the T-ASIC contains all possible triggers. For normal
triggering, the T-ASIC uses ALLTRIG to generate the final trigger TRIGDT. For
qualified triggering (e.g. TV triggering), the D-ASIC returns a qualified, e.g. each n
trigger pulse to the T-ASIC (TRIGQUAL). Now the T-ASIC derives the final trigger
TRIGDT from the qualified trigger signal TRIGQUAL.
Capacitance measurements (ALLTRIG)
As described in Section 3.3.2, capacitance measurements are based on measuring the
capacitor charging time using a known current. The ALLTRIG pulse signal represents
the charging time. The time is counted by the D-ASIC
Microprocessor
The D-ASIC includes a microprocessor with a 16 bit data bus. The instrument software
is loaded in a 8 Mb Flash ROM D474.
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