Fluke ScopeMeter 123 Service Manual page 47

Triggering
Figure 3-10 shows the block diagram of the T-ASIC trigger section.
10
TRIGLEV1
11
TRIGLEV2
13
TRIG A
15
TRIG B
16
TVSYNC
Figure 3-10. T-ASIC Trigger Section Block Diagram
In normal trigger modes (= not TV triggering), the analog trigger path directly uses the
Input A (TRIG A) or Input B (TRIG B) signal for triggering.
In the TV trigger mode, the analog trigger path uses the TVSYNC signal for triggering.
This signal is the synchronization pulse, derived from the TRIGA or TRIGB composite
video signal. The color filter +/- amplify section in the T-ASIC blocks the color
information, and amplifies and inverts (if required) the video signal. The TVOUT output
signal is supplied to the synchronization pulse separator circuit. This circuit consists of
C395, V395 and related parts. The output signal TVSYNC is the synchronization pulse
at the appropriate voltage level and amplitude for the T-ASIC analog trigger path.
External triggers provided by the Isolated Trigger Probe to the optical
interface are processed directly by the D-ASIC.
The TRIG-A, TRIG-B, or TVSYNC signal, and two trigger level voltages TRIGLEV1
and TRIGLEV2, are supplied to the analog trigger part. The trigger level voltages are,
supplied by the PWM section on the Digital part See Section 3.3.4). The TRIGLEV1
voltage is used for triggering on a negative slope of the Input A/B voltage. The
TRIGLEV2 voltage is used for triggering on a positive slope of the Input A/B voltage.
As the C-ASIC inverts the Input A/B voltage, the TRIGA, TRIGB slopes on the T-ASIC
input are inverted! From the selected trigger source signal and the used trigger level
voltages, the ALLTRIG and the DUALTRIG trigger signal are derived. The select logic
selects which one will be used by the synchronization/delta-T circuit to generate the final
trigger. There are three possibilities:
1. Single shot triggering.
The DUALTRIG signal is supplied to the synchronization/delta-T circuit. The
trigger levels TRIGLEV1 and TRIGLEV2 are set just above and below the DC level
of the input signal. A trigger is generated when the signal crosses the trigger levels.
A trigger will occur on both a positive or a negative glitch. This mode ensures
triggering, when the polarity of an expected glitch is not known.
2. Qualified triggering (e.g. TV triggering).
The ALLTRIG signal is supplied to T-ASIC output pin 35, which is connected to the
D-ASIC input pin 21. The D-ASIC derives a qualified trigger signal TRIGQUAL
TRIGGER ASIC OQ0257 trigger section
ALLTRIG
analog
DUALTRIG
trigger path
colour filter
+/- amplifier
12
TVOUT
sync. pulse
separator
Note
3.3 Detailed Circuit Descriptions
35
42
select synchronize
34
logic delta-t
39
38
freq. 29
detect
Circuit Descriptions
ALLTRIG
TRIGQUAL
TRIGDT
HOLDOFF
SMPCLK
DACTEST
3-21
3