Fluke ScopeMeter 123 Service Manual page 43

3
Circuit Descriptions
3.3 Detailed Circuit Descriptions
CALSIG input pin 36
The reference circuit on the TRIGGER part supplies an accurate +1.23V DC voltage to
the CALSIG input pin 36 via R141. This voltage is used for internal calibration of the
gain, and the capacitance measurement threshold levels. A reference current Ical is
supplied by the T-ASIC via R144 for calibration of the resistance and capacitance
measurement function. For ICAL see also Section 3.3.3.
POS input pin 1
The PWM circuit on the Digital part provides an adjustable voltage (0 to 3.3V) to the
POS input via R151. The voltage level is used to move the input signal trace on the
LCD. The REFN line provides a negative bias voltage via R152, to create the correct
voltage swing level on the C-ASIC POS input.
OFFSET input pin 44
The PWM circuit on the Digital part supplies an adjustable voltage (0 to +3.3V) to the
OFFSET input via R153. The voltage level is used to compensate the offset in the LF
path of the C-ASIC. The REFN line provides a negative bias voltage via R152, to create
the correct voltage swing level on the C-ASIC POS input.
DACTEST output pin 24
As described above, the DACTEST output is used for signaling a ground protect error. It
can also be used for testing purposes. Furthermore the DACTEST output provides a C-
ASIC reset output signal (+1.75V) after a power on.
ADDRESS output pin 23
The output provides a replica of the input voltage to the SENSE line via R165. In
capacitance mode, the sense signal controls the CLAMP function in the T-ASIC (See
Section 3.3.3).
TRACEROT input pin 31
The TRACEROT signal is supplied by the T-ASIC. It is a triangle sawtooth voltage.
SDAT, SCLK
Control information for the C-ASIC, e.g. selection of the attenuation factor, is sent by the
D-ASIC via the SDA data line. The SCL line provides the synchronization clock signal.
Voltage Measurements (Channel A & Channel B)
The following description applies to both Channel A and Channel B.
The input voltage is applied to the HF attenuator inputs of the C-ASIC via C104, and to
the LF input of the C-ASIC via R101/R102, AC/DC input coupling relay K171, and
R104. The C-ASIC conditions the input voltage to an output voltage of 50 mV/div. This
voltage is supplied to the ADC on the Digital part. The ADC output data is read and
processed by the D-ASIC, and represented as a numerical reading, and as a graphical
trace.
Table 3-3. shows the relation between the reading range (V) and the trace sensitivity
(V/div.) The selected trace sensitivity determines the C-ASIC attenuation/gain factor.
The reading range is only a readout function, it does not change the hardware range or
the wave form display.
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