Texas Instruments ADS5517 User Manual
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Texas Instruments ADS5517 User Manual

Texas Instruments ADS5517 User Manual

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ADS5517/25/27/45/46/47 EVM User
Guide
User's Guide
January 2008
SLWU028C

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Summary of Contents for Texas Instruments ADS5517

  • Page 1 ADS5517/25/27/45/46/47 EVM User Guide User's Guide January 2008 SLWU028C...
  • Page 2 SLWU028C – January 2006 – Revised January 2008 Submit Documentation Feedback...

  • Page 3: Table Of Contents

    Contents ........................Overview .................... EVM Basic Functions ....................EVM Quick Start Guide .............. EVM LVDS Output Mode Quick Start (Default) ................ EVM CMOS Output Mode Quick Start ...................... Circuit Description ....................Schematic Diagram ....................Circuit Function ....................Expansion Options ................... Custom FPGA Code ....................
  • Page 4 List of Figures ................ADS5547 SNR Performance vs Decoupling ................THS4509 + ADS5545 EVM Performance ..................Eye Diagram of Data on Header J4........................Top Layer ....................Layer 2, Ground Plane ....................Layer 3, Power Plane #1 ....................Layer 4, Power Plane #2 ....................

  • Page 5: Overview

    SLWU028C – January 2006 – Revised January 2008 Overview This manual assists users in using the ADS5517/25/27/45/46/47 evaluation module (EVM) for evaluating the performance of the ADS5517/25/27/45/46/47 (ADCs). The EVM provides a powerful and robust capability in evaluation of the many features of the ADCs and the performance of the device under many conditions.

  • Page 6: Evm Quick Start Guide

    www.ti.com EVM Quick Start Guide EVM Quick Start Guide The ADC has two basic modes of output operation, ensuring compatibility in a broad range of systems. Follow the steps below to get the EVM operating quickly with the ADC in either DDR LVDS output mode or CMOS output mode.

  • Page 7: Circuit Description

    www.ti.com Circuit Description Circuit Description Schematic Diagram The schematic diagram for the EVM is in Section 5.3 of this document. Circuit Function The following paragraphs describe the function of individual circuits. See the data sheet for complete device operating characteristics. 3.2.1 Configuration Options The EVM provides a DIP switch, SW1, to control many of the modes of operation when the EVM is...

  • Page 8: Ads5547 Snr Performance Vs Decoupling

    www.ti.com Circuit Description Table 2. EVM Power Options BANANA JACK NAME VOLTAGE DESCRIPTION Device AGND AGND Device AVDD Device analog supply Amplifier negative –5 THS4509 Vs– supply rail Amplifier positive rail THS4509 Vs+ supply Auxiliary power Supplies power to all peripheral circuitry including the FPGA and PROM.
  • Page 9 www.ti.com Circuit Description The schematics present various interface options between the amplifier and the ADC. Depending on the input frequencies of interest, further performance optimization can be had by designing a corresponding filter. In its default configuration, R43, R44, and C119 form a first-order, low-pass filter with a cutoff frequency of 70 MHz.

  • Page 10: Output Connector J4

    Circuit Description Table 3. Output Connector J4 J4 PIN ADS5517 ADS5525/27 ADS5545/46/47 DESCRIPTION DESCRIPTION DESCRIPTION Reserved Reserved Reserved Reserved Reserved Reserved Data bit 0 (LSB) Data bit 1 Data bit 0 (LSB) Data bit 2 Data bit 0 (LSB)

  • Page 11: Eye Diagram Of Data On Header J4

    www.ti.com Circuit Description C001 Figure 3. Eye Diagram of Data on Header J4. 3.2.6 Test Points For added EVM visibility and control, several test points are provided. Table 4 summarizes the test points available. SLWU028C – January 2006 – Revised January 2008 Submit Documentation Feedback...

  • Page 12: Test Points

    www.ti.com Circuit Description Table 4. Test Points DESCRIPTION ADC common mode, input or output depending on the setting of SW1, switch 4 THS4509 power down ADC output enable AGND AGND AGND DGND FPGA M0 pin; determines which FPGA logic file to load TP10 ADC SCLK TP11...

  • Page 13: Expansion Options

    www.ti.com Expansion Options Expansion Options The EVM offers several exciting possibilities to expand the capabilities of the EVM. This allows the utmost flexibility when prototyping an ADC circuit under conditions that mimic the end system, without the need to develop a custom prototype board. Custom FPGA Code Using a standard JTAG interface on JP1, users have the ability to load custom logic onto the FPGA, rapidly speeding up digital development time.

  • Page 14: Physical Description

    www.ti.com Physical Description Physical Description This chapter describes the physical characteristics and PCB layout of the EVM. PCB Layout The EVM is constructed on a 6-layer, 0.062-inch thick PCB using FR-4 material. The individual layers are shown in Figure 4 through Figure 9.

  • Page 15: Layer 2, Ground Plane

    www.ti.com Physical Description K002 Figure 5. Layer 2, Ground Plane SLWU028C – January 2006 – Revised January 2008 Submit Documentation Feedback...

  • Page 16: Layer 3, Power Plane #1

    www.ti.com Physical Description K003 Figure 6. Layer 3, Power Plane #1 SLWU028C – January 2006 – Revised January 2008 Submit Documentation Feedback...

  • Page 17: Layer 4, Power Plane #2

    www.ti.com Physical Description K004 Figure 7. Layer 4, Power Plane #2 SLWU028C – January 2006 – Revised January 2008 Submit Documentation Feedback...

  • Page 18: Layer 5, Ground Plane

    www.ti.com Physical Description K005 Figure 8. Layer 5, Ground Plane SLWU028C – January 2006 – Revised January 2008 Submit Documentation Feedback...

  • Page 19: Layer 6, Bottom Layer

    www.ti.com Physical Description K006 Figure 9. Layer 6, Bottom Layer SLWU028C – January 2006 – Revised January 2008 Submit Documentation Feedback...

  • Page 20: Bill Of Materials

    www.ti.com Physical Description Bill of Materials The bill of materials appears on the following page. SLWU028C – January 2006 – Revised January 2008 Submit Documentation Feedback...
  • Page 21 www.ti.com Physical Description Table 5. Bill of Materials VALUE FOOTPRINT PART NUMBER VENDOR DIGI-KEY NUMBER REF DESIGNATOR INSTALLED CAPACITORS 47-µF, tantalum, 20%, 10-V 7343 ECS-T1AD476R Panasonic PCS2476CT-ND C65, C66, C68, C69 10-µF, 10-V, 20% 3528 ECS-T1AX106R Panasonic PCS2106CT-ND C70, C71, C72, C73, 10-µF, 10-V, 20% 3216 ECS-T1AY106R...
  • Page 22 www.ti.com Physical Description Table 5. Bill of Materials (continued) VALUE FOOTPRINT PART NUMBER VENDOR DIGI-KEY NUMBER REF DESIGNATOR INSTALLED RESISTORS 0-Ω, 1/10-W, 5% ERJ-3GEY0R00V Panasonic P0.0GCT-ND R5, R6, R10, R18, R54, R56 R48, R58, R82 0-Ω, 1/10-W, 5% ERJ-GE0R00X Panasonic P0.0JCT-ND R11, C45, C47 4.02-Ω, 1/10-W 1%...
  • Page 23 www.ti.com Physical Description Table 5. Bill of Materials (continued) VALUE FOOTPRINT PART NUMBER VENDOR DIGI-KEY NUMBER REF DESIGNATOR INSTALLED FERRITE BEADS, CONNECTORS, JUMPERS, JACKS, ICs, ETC. Ferrite bead 1206 EXC-ML32A680U Panasonic P10437CT-ND FB2, FB3, FB4, FB6, FB8, FB9, FB10 Inductor, SMT, 15-µH, 2.6-A COIL-CDRH8D43 CDRH8D43-150 Sumida...
  • Page 24 Physical Description Table 5. Bill of Materials (continued) VALUE FOOTPRINT PART NUMBER VENDOR DIGI-KEY NUMBER REF DESIGNATOR INSTALLED ADS5517/25/27, 48-QFN_MOD ADS5517/25/27, ADS5545/46/47 ADS5545/46/47 Spartan-3E XC3S250E 256-BGA- XC3S250E-4FT256CES Xilinx 1mm_XILINX IC amp, fully-diff, wideband 16-QFN(RGT) THS4509RGTT 296-17730-1-ND XCF16PFSG48 48PIN_BGA_XILINX XCF16PFSG48...

  • Page 25: Pcb Schematics

    www.ti.com Physical Description PCB Schematics The schematics for the EVM are on the following pages. SLWU028C – January 2006 – Revised January 2008 Submit Documentation Feedback...

  • Page 26: Important Notices

    XILINX XC3S500E_FT256 2.5V VCCO_0 IO_L01N_0 VCCO_0 IO_L01P_0 VCCO_0 IO_L03N_0/VREF_0 VCCO_0 IO_L03P_0 VCCO_0 2.5V IO_L04N_0 (1-2) IO_L04P_0 3.3V DRVDD IO_L05N_0/VREF_0 IO_L05P_0 IO_L06N_0 IO_L06P_0 IO_L12N_0 .1uF .1uF 10uF IO_L12P_0 CLKOUTM IO_L08N_0/GCLK5 CLKOUTP IO_L08P_0/GCLK4 D12_D13P IO_L09N_0/GCLK7 D12_D13M IO_L09P_0/GCLK6 D10_D11P IP_L10N_0/GCLK9 D10_D11M IP_L10P_0/GCLK8 D8_D9P IO_L11N_0/GCLK11 D8_D9M IO_L11P_0/GCLK10...
  • Page 27 +VCC AMPLIFIER PATH: AC Couple (default) .1uF .1uF 10uF 10uF C45 C47 = 0.1uF R26 R27 = 200 Ohms R5 = 0 Ohms VCC= 5 V, VEE = GND DC Couple C45 C47 = 0 Ohms SMA_END .1uF R26 R27 = Unpopulated R5 = Unpopulated AMP_P VCC= 4 V, VEE = -1V...
  • Page 28 (Note 1) CLK_INP .1uF 49.9 SJP2 (Note 1) TC4-1W CLKP CLKP (Sh 1) CLK_INM (1-2) (Note 1) .1uF (Note 1) CLKM SJP1 CLKM (Sh 1) (1-2) 12500 TI Boulevard. Dallas, Texas 75243 Title: ADS5545 Engineer: J. VENABLE DOCUMENTCONTROL # Note 1. Part not installed REV: Drawn By: Y.
  • Page 29 XILINX XC3S500E_FT256 3.3V 40PIN_IDC CLKOUT IO_L01N_1/A15 VCCO_1 20 Ohm IO_L01P_1/A16 VCCO_1 ADC_D0 IO_L02N_1/A13 VCCO_1 ADC_D1 IO_L02P_1/A14 VCCO_1 ADC_D2 IO_L04N_1/VREF_1 ADC_D3 XILINX XC3S500E_FT256 3.3V IO_L04P_1 ADC_D4 IO_L06N_1 ADC_D5 ADC_D6 IO_L06P_1 IO_L19N_3 VCCO_3 ADC_D6 ADC_D5 IO_L09N_1/A9/RHCLK1 IO_L19P_3 VCCO_3 ADC_D7 ADC_D4 IO_L09P_1/A10/RHCLK0 IO_L18N_3 VCCO_3 ADC_D8 ADC_D3...
  • Page 30 3.3V 2.5V LED_1206 4.75K 2.5V 1.8V XCF16PFSG48 INIT_B DTC114EET1 VCCINT OE/RESET__ INIT_B (Sh 4) VCCINT CCLK 4.75K XILINX XC3S500E_FT256 1.2V VCCINT CCLK (Sh 4) CE__ BUSY DONE BUSY BUSY (Sh 4) DONE VCCINT VCCINT 3.3V PROG_B CLKOUT PROG_B VCCINT VCCINT VCCINT VCCO VCCINT...
  • Page 31 1.2V VCCO_0 BANK 0 DECOUPLING CDRH8D43-150 15uH 100uF FET-SI2323DS SS32 2.2uF .22uF .22uF .022uF .022uF .01uF 1.5nF 1.5nF .033 TP11 .1uF 3.3V BANK 1 DECOUPLING C100 100uF 2.2uF .22uF .22uF .022uF .022uF 2.5V TPS75003 OUT3 1.2V 3.3V BANK 2 DECOUPLING 10uF 3.3V 61.9K...
  • Page 32 Diff Amp Positive Supply (+5.0V) +VCC ADC Analog Supply (+3.3V) .1uF +3.3VA-PS 47uF 10uF AVDD BLACK .1uF Diff Amp Negative Supply (-5.0V) .1uF 47uF 10uF -VCC BLACK .1uF 47uF 10uF ADC DIGITAL SUPPLY(3.3V) FPGA POWER SUPPLY(5V) OUTPUT_BUFFER DRVDD .1uF .1uF .1uF 47uF 10uF...
  • Page 33 EVALUATION BOARD/KIT IMPORTANT NOTICE Texas Instruments (TI) provides the enclosed product(s) under the following conditions: This evaluation board/kit is intended for use for ENGINEERING DEVELOPMENT, DEMONSTRATION, OR EVALUATION PURPOSES ONLY and is not considered by TI to be a finished end-product fit for general consumer use. Persons handling the product(s) must have electronics training and observe good engineering practice standards.
  • Page 34 Mouser Electronics Authorized Distributor Click to View Pricing, Inventory, Delivery & Lifecycle Information: Texas Instruments ADS5545EVM ADS5517EVM...

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