Ths4509 + Ads5545 Evm Performance - Texas Instruments 27 User Manual

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The schematics present various interface options between the amplifier and the ADC. Depending on
the input frequencies of interest, further performance optimization can be had by designing a
corresponding filter. In its default configuration, R43, R44, and C119 form a first-order, low-pass filter
with a cutoff frequency of 70 MHz.
THS4509 path.
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3.2.4 Clock Input
A single-ended, harmonically filtered, low-phase-noise, 1.5-Vrms sinusoidal input should be applied to J7.
The frequency must not exceed the device specification. In the EVM default configuration, both SPJ1 and
SJP2 must have pins 1 and 2 shorted.
In the board default configuration, the transformer provides single-ended to differential conversion. The
transformer has an impedance ratio of 4.
3.2.5 Digital Outputs
For compatibility with a broad range of logic analyzers, the EVM outputs 3.3-V parallel CMOS data on
header J4, independent of the ADC operational mode. The Xilinx™Spartan™-3E FPGA provides the
necessary translation, and it configures itself using one of two different logic files stored in the PROM,
based on the EVM configuration. The CMOS data output of the FPGA is contained in data header J4 and
is a standard 40-pin header on a 100-mil grid, which allows easy connection to a logic analyzer. The
connector pinout is listed in
hold-time adjustments must be made to the logic analyzer if using the rising edge of the output clock to
latch in the data.
Note: The eye diagram shown is the output of the FPGA at 210 MSPS, not that of the ADC. For
the ADC output timing, see the respective device data sheet.
SLWU028B – January 2006 – Revised November 2006
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Figure 2
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f − Frequency − MHz
Figure 2. THS4509 + ADS5545 EVM Performance
Table 3. For quick setup, the eye diagram is shown in
shows the performance of the ADS5545 using the
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40 45 50 55 60
Circuit Description
x
65 70 75 80 85
G002
Figure 3. No setup or
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